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authorAndreas Hansson <andreas.hansson@arm.com>2014-12-02 06:07:46 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2014-12-02 06:07:46 -0500
commit3d6ec81e6612547efa22507f6e82d5d9c7d75252 (patch)
tree91121b35973ca1eb671e8d7579e75ea2ebbe6742 /src/mem/cache
parent41846cb61b0f511099eb9a203f11885de328ab45 (diff)
downloadgem5-3d6ec81e6612547efa22507f6e82d5d9c7d75252.tar.xz
mem: Add checks and explanation for assertMemInhibit usage
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 2eb38805c..535dc81c2 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1693,7 +1693,12 @@ Cache<TagStore>::handleSnoop(PacketPtr pkt, BlkType *blk,
}
if (respond) {
- assert(!pkt->memInhibitAsserted());
+ // prevent anyone else from responding, cache as well as
+ // memory, and also prevent any memory from even seeing the
+ // request (with current inhibited semantics), note that this
+ // applies both to reads and writes and that for writes it
+ // works thanks to the fact that we still have dirty data and
+ // will write it back at a later point
pkt->assertMemInhibit();
if (have_exclusive) {
pkt->setSupplyExclusive();