diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
| commit | 19a5b68db7d73542833d94ec8b23cad6daf0a787 (patch) | |
| tree | 589541b322580a54e539e24932d3b4bba05801db /src/mem/cache | |
| parent | ea402970185d5df01dbad2c0f41b8d76d2eb01cd (diff) | |
| download | gem5-19a5b68db7d73542833d94ec8b23cad6daf0a787.tar.xz | |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/SConscript | 3 | ||||
| -rw-r--r-- | src/mem/cache/base.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/SConscript | 2 | ||||
| -rw-r--r-- | src/mem/cache/tags/SConscript | 3 | ||||
| -rw-r--r-- | src/mem/cache/tags/base.cc | 1 |
5 files changed, 1 insertions, 10 deletions
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 8323602d2..a4fbe04c0 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -30,9 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() - SimObject('BaseCache.py') Source('base.cc') diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 03b4d5dc1..af324527f 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -45,8 +45,6 @@ * Definition of BaseCache functions. */ -#include "cpu/base.hh" -#include "cpu/smt.hh" #include "debug/Cache.hh" #include "debug/Drain.hh" #include "mem/cache/tags/fa_lru.hh" diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index 2310940c1..61291f715 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -30,8 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() SimObject('Prefetcher.py') Source('base.cc') diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index de835c1d0..dca8d3bd8 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -30,9 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() - SimObject('Tags.py') Source('base.cc') diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc index d9909f5de..947bd05de 100644 --- a/src/mem/cache/tags/base.cc +++ b/src/mem/cache/tags/base.cc @@ -46,6 +46,7 @@ * Definitions of BaseTags. */ +#include "config/the_isa.hh" #include "cpu/smt.hh" //maxThreadsPerCPU #include "mem/cache/tags/base.hh" #include "mem/cache/base.hh" |