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authorRon Dreslinski <rdreslin@umich.edu>2007-03-12 15:59:54 -0500
committerRon Dreslinski <rdreslin@umich.edu>2007-03-12 15:59:54 -0500
commit2a02087eb52e12e16e9da74e929e875ae07519ec (patch)
tree1a65351bfc32ee341817a557d7c69337e0e75d84 /src/mem/cache
parentca8e95b480bfef4b97e54e22b0cbb8e8ec9513f4 (diff)
downloadgem5-2a02087eb52e12e16e9da74e929e875ae07519ec.tar.xz
Clean up more memory leaks
--HG-- extra : convert_revision : 32d1b23200752fe5fcdcbafb586f50bbe6db3bf3
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh13
1 files changed, 4 insertions, 9 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d8aab0e58..5c6ab0950 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -583,12 +583,7 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
// Hit
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
// clear dirty bit if write through
- if (pkt->needsResponse())
- respond(pkt, curTick+lat);
- if (pkt->cmd == MemCmd::Writeback) {
- //Signal that you can kill the pkt/req
- pkt->flags |= SATISFIED;
- }
+ respond(pkt, curTick+lat);
return true;
}
@@ -606,14 +601,14 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
if (pkt->flags & SATISFIED) {
// happens when a store conditional fails because it missed
// the cache completely
- if (pkt->needsResponse())
- respond(pkt, curTick+lat);
+ respond(pkt, curTick+lat);
} else {
missQueue->handleMiss(pkt, size, curTick + hitLatency);
}
- if (pkt->cmd == MemCmd::Writeback) {
+ if (!pkt->needsResponse()) {
//Need to clean up the packet on a writeback miss, but leave the request
+ //for the next level.
delete pkt;
}