Small bug fixes for timing LL/SC. Better now but

not necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f

1 files changed, 6 insertions, 1 deletions

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 64f658907..3c47762f6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -232,7 +232,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
         }
     }
 
-    if (!(pkt->flags & SATISFIED)) {
+    if (pkt->flags & SATISFIED) {
+        // happens when a store conditional fails because it missed
+        // the cache completely
+        if (pkt->needsResponse())
+            respond(pkt, curTick+lat);
+    } else {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
     }