diff options
author | Steve Reinhardt <stever@gmail.com> | 2008-02-11 08:31:26 -0800 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2008-02-11 08:31:26 -0800 |
commit | 71835d42df8fb488380be8cc89be4298b268902a (patch) | |
tree | 7c2e91d34de4a2306f45234fefa13ded7ea5d83f /src/mem/cache | |
parent | 2f7421b12b4a557ff1a2e4dcebcfd3484778fb95 (diff) | |
parent | 4c7eb211191055f72c6f157913cb384f47cf4334 (diff) | |
download | gem5-71835d42df8fb488380be8cc89be4298b268902a.tar.xz |
Automated merge with file:/home/stever/hg/m5-orig
--HG--
extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
Diffstat (limited to 'src/mem/cache')
-rw-r--r-- | src/mem/cache/SConscript | 8 | ||||
-rw-r--r-- | src/mem/cache/base.cc (renamed from src/mem/cache/base_cache.cc) | 4 | ||||
-rw-r--r-- | src/mem/cache/base.hh (renamed from src/mem/cache/base_cache.hh) | 2 | ||||
-rw-r--r-- | src/mem/cache/blk.cc (renamed from src/mem/cache/cache_blk.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/blk.hh (renamed from src/mem/cache/cache_blk.hh) | 0 | ||||
-rw-r--r-- | src/mem/cache/builder.cc (renamed from src/mem/cache/cache_builder.cc) | 8 | ||||
-rw-r--r-- | src/mem/cache/cache.hh | 6 | ||||
-rw-r--r-- | src/mem/cache/cache_impl.hh | 6 | ||||
-rw-r--r-- | src/mem/cache/mshr.cc (renamed from src/mem/cache/miss/mshr.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/mshr.hh (renamed from src/mem/cache/miss/mshr.hh) | 0 | ||||
-rw-r--r-- | src/mem/cache/mshr_queue.cc (renamed from src/mem/cache/miss/mshr_queue.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/mshr_queue.hh (renamed from src/mem/cache/miss/mshr_queue.hh) | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/SConscript | 8 | ||||
-rw-r--r-- | src/mem/cache/prefetch/base.cc (renamed from src/mem/cache/prefetch/base_prefetcher.cc) | 4 | ||||
-rw-r--r-- | src/mem/cache/prefetch/base.hh (renamed from src/mem/cache/prefetch/base_prefetcher.hh) | 0 | ||||
-rw-r--r-- | src/mem/cache/prefetch/ghb.cc (renamed from src/mem/cache/prefetch/ghb_prefetcher.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/ghb.hh (renamed from src/mem/cache/prefetch/ghb_prefetcher.hh) | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/stride.cc (renamed from src/mem/cache/prefetch/stride_prefetcher.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/stride.hh (renamed from src/mem/cache/prefetch/stride_prefetcher.hh) | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/tagged.cc (renamed from src/mem/cache/prefetch/tagged_prefetcher.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/prefetch/tagged.hh (renamed from src/mem/cache/prefetch/tagged_prefetcher.hh) | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/Repl.py | 11 | ||||
-rw-r--r-- | src/mem/cache/tags/SConscript | 6 | ||||
-rw-r--r-- | src/mem/cache/tags/base.cc (renamed from src/mem/cache/tags/base_tags.cc) | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/base.hh (renamed from src/mem/cache/tags/base_tags.hh) | 0 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.hh | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/iic.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/iic.hh | 6 | ||||
-rw-r--r-- | src/mem/cache/tags/iic_repl/Repl.py (renamed from src/mem/cache/miss/SConscript) | 17 | ||||
-rw-r--r-- | src/mem/cache/tags/iic_repl/gen.cc (renamed from src/mem/cache/tags/repl/gen.cc) | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/iic_repl/gen.hh (renamed from src/mem/cache/tags/repl/gen.hh) | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/iic_repl/repl.hh (renamed from src/mem/cache/tags/repl/repl.hh) | 0 | ||||
-rw-r--r-- | src/mem/cache/tags/lru.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/lru.hh | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/split.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/split.hh | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/split_blk.hh | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lifo.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lifo.hh | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lru.cc | 2 | ||||
-rw-r--r-- | src/mem/cache/tags/split_lru.hh | 4 |
41 files changed, 71 insertions, 75 deletions
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index d5899b623..3b8bdb0c8 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -32,10 +32,12 @@ Import('*') SimObject('BaseCache.py') -Source('base_cache.cc') +Source('base.cc') Source('cache.cc') -Source('cache_blk.cc') -Source('cache_builder.cc') +Source('blk.cc') +Source('builder.cc') +Source('mshr.cc') +Source('mshr_queue.cc') TraceFlag('Cache') TraceFlag('CachePort') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base.cc index 9fa9e2d29..ac0d54bf6 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base.cc @@ -35,8 +35,8 @@ #include "cpu/base.hh" #include "cpu/smt.hh" -#include "mem/cache/base_cache.hh" -#include "mem/cache/miss/mshr.hh" +#include "mem/cache/base.hh" +#include "mem/cache/mshr.hh" using namespace std; diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base.hh index 604474524..d97021024 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base.hh @@ -47,7 +47,7 @@ #include "base/misc.hh" #include "base/statistics.hh" #include "base/trace.hh" -#include "mem/cache/miss/mshr_queue.hh" +#include "mem/cache/mshr_queue.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/tport.hh" diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/blk.cc index d4a2eaee8..4952ed758 100644 --- a/src/mem/cache/cache_blk.cc +++ b/src/mem/cache/blk.cc @@ -27,7 +27,7 @@ */ #include "base/cprintf.hh" -#include "mem/cache/cache_blk.hh" +#include "mem/cache/blk.hh" void CacheBlkPrintWrapper::print(std::ostream &os, int verbosity, diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/blk.hh index bafb46a89..bafb46a89 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/blk.hh diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/builder.cc index d67a9c9a4..db900c64c 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/builder.cc @@ -39,7 +39,7 @@ #include "enums/Prefetch.hh" #include "mem/config/cache.hh" #include "mem/config/prefetch.hh" -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "mem/cache/cache.hh" #include "mem/bus.hh" #include "params/BaseCache.hh" @@ -67,13 +67,13 @@ //Prefetcher Headers #if defined(USE_GHB) -#include "mem/cache/prefetch/ghb_prefetcher.hh" +#include "mem/cache/prefetch/ghb.hh" #endif #if defined(USE_TAGGED) -#include "mem/cache/prefetch/tagged_prefetcher.hh" +#include "mem/cache/prefetch/tagged.hh" #endif #if defined(USE_STRIDED) -#include "mem/cache/prefetch/stride_prefetcher.hh" +#include "mem/cache/prefetch/stride.hh" #endif diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 170ba0cd1..073ce5ecb 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -41,9 +41,9 @@ #include "base/misc.hh" // fatal, panic, and warn -#include "mem/cache/base_cache.hh" -#include "mem/cache/cache_blk.hh" -#include "mem/cache/miss/mshr.hh" +#include "mem/cache/base.hh" +#include "mem/cache/blk.hh" +#include "mem/cache/mshr.hh" #include "sim/eventq.hh" diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 7a06f9fc7..6e4b50ed9 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -42,9 +42,9 @@ #include "base/range_ops.hh" #include "mem/cache/cache.hh" -#include "mem/cache/cache_blk.hh" -#include "mem/cache/miss/mshr.hh" -#include "mem/cache/prefetch/base_prefetcher.hh" +#include "mem/cache/blk.hh" +#include "mem/cache/mshr.hh" +#include "mem/cache/prefetch/base.hh" #include "sim/sim_exit.hh" // for SimExitEvent diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/mshr.cc index d711ca537..6537f6343 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/mshr.cc @@ -39,7 +39,7 @@ #include <vector> #include <algorithm> -#include "mem/cache/miss/mshr.hh" +#include "mem/cache/mshr.hh" #include "sim/core.hh" // for curTick #include "sim/host.hh" #include "base/misc.hh" diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/mshr.hh index fdb0485cb..fdb0485cb 100644 --- a/src/mem/cache/miss/mshr.hh +++ b/src/mem/cache/mshr.hh diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/mshr_queue.cc index 71da7e4c1..45331c33d 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/mshr_queue.cc @@ -32,7 +32,7 @@ * Definition of MSHRQueue class functions. */ -#include "mem/cache/miss/mshr_queue.hh" +#include "mem/cache/mshr_queue.hh" using namespace std; diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/mshr_queue.hh index e04745087..f481ca471 100644 --- a/src/mem/cache/miss/mshr_queue.hh +++ b/src/mem/cache/mshr_queue.hh @@ -38,7 +38,7 @@ #include <vector> #include "mem/packet.hh" -#include "mem/cache/miss/mshr.hh" +#include "mem/cache/mshr.hh" /** * A Class for maintaining a list of pending and allocated memory requests. diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index 8a7f1232c..7314b5ccf 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -30,8 +30,8 @@ Import('*') -Source('base_prefetcher.cc') -Source('ghb_prefetcher.cc') -Source('stride_prefetcher.cc') -Source('tagged_prefetcher.cc') +Source('base.cc') +Source('ghb.cc') +Source('stride.cc') +Source('tagged.cc') diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base.cc index 1af900849..fcc02ff28 100644 --- a/src/mem/cache/prefetch/base_prefetcher.cc +++ b/src/mem/cache/prefetch/base.cc @@ -34,8 +34,8 @@ */ #include "base/trace.hh" -#include "mem/cache/base_cache.hh" -#include "mem/cache/prefetch/base_prefetcher.hh" +#include "mem/cache/base.hh" +#include "mem/cache/prefetch/base.hh" #include "mem/request.hh" #include <list> diff --git a/src/mem/cache/prefetch/base_prefetcher.hh b/src/mem/cache/prefetch/base.hh index 1515d8a93..1515d8a93 100644 --- a/src/mem/cache/prefetch/base_prefetcher.hh +++ b/src/mem/cache/prefetch/base.hh diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb.cc index d7d819a2d..f5b88e1a6 100644 --- a/src/mem/cache/prefetch/ghb_prefetcher.cc +++ b/src/mem/cache/prefetch/ghb.cc @@ -34,7 +34,7 @@ * GHB Prefetcher implementation. */ -#include "mem/cache/prefetch/ghb_prefetcher.hh" +#include "mem/cache/prefetch/ghb.hh" #include "arch/isa_traits.hh" void diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb.hh index c44e9c456..4fb692016 100644 --- a/src/mem/cache/prefetch/ghb_prefetcher.hh +++ b/src/mem/cache/prefetch/ghb.hh @@ -36,7 +36,7 @@ #ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__ #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__ -#include "mem/cache/prefetch/base_prefetcher.hh" +#include "mem/cache/prefetch/base.hh" class GHBPrefetcher : public BasePrefetcher { diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride.cc index 8d957182a..b116b66c7 100644 --- a/src/mem/cache/prefetch/stride_prefetcher.cc +++ b/src/mem/cache/prefetch/stride.cc @@ -34,7 +34,7 @@ * Stride Prefetcher template instantiations. */ -#include "mem/cache/prefetch/stride_prefetcher.hh" +#include "mem/cache/prefetch/stride.hh" void StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride.hh index 4d5ac2f0d..f6bdbc424 100644 --- a/src/mem/cache/prefetch/stride_prefetcher.hh +++ b/src/mem/cache/prefetch/stride.hh @@ -36,7 +36,7 @@ #ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ #define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ -#include "mem/cache/prefetch/base_prefetcher.hh" +#include "mem/cache/prefetch/base.hh" class StridePrefetcher : public BasePrefetcher { diff --git a/src/mem/cache/prefetch/tagged_prefetcher.cc b/src/mem/cache/prefetch/tagged.cc index b25cb5054..6afe1c6c2 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher.cc +++ b/src/mem/cache/prefetch/tagged.cc @@ -34,7 +34,7 @@ */ #include "arch/isa_traits.hh" -#include "mem/cache/prefetch/tagged_prefetcher.hh" +#include "mem/cache/prefetch/tagged.hh" TaggedPrefetcher::TaggedPrefetcher(const BaseCacheParams *p) : BasePrefetcher(p), diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged.hh index f3094445f..78e20083d 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher.hh +++ b/src/mem/cache/prefetch/tagged.hh @@ -36,7 +36,7 @@ #ifndef __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__ #define __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__ -#include "mem/cache/prefetch/base_prefetcher.hh" +#include "mem/cache/prefetch/base.hh" class TaggedPrefetcher : public BasePrefetcher { diff --git a/src/mem/cache/tags/Repl.py b/src/mem/cache/tags/Repl.py deleted file mode 100644 index b76aa1d6e..000000000 --- a/src/mem/cache/tags/Repl.py +++ /dev/null @@ -1,11 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class Repl(SimObject): - type = 'Repl' - abstract = True - -class GenRepl(Repl): - type = 'GenRepl' - fresh_res = Param.Int("Fresh pool residency time") - num_pools = Param.Int("Number of priority pools") - pool_res = Param.Int("Pool residency time") diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index 18ed8408b..9153d97e7 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -30,7 +30,7 @@ Import('*') -Source('base_tags.cc') +Source('base.cc') Source('fa_lru.cc') Source('iic.cc') Source('lru.cc') @@ -38,8 +38,8 @@ Source('split.cc') Source('split_lifo.cc') Source('split_lru.cc') -SimObject('Repl.py') -Source('repl/gen.cc') +SimObject('iic_repl/Repl.py') +Source('iic_repl/gen.cc') TraceFlag('IIC') TraceFlag('IICMore') diff --git a/src/mem/cache/tags/base_tags.cc b/src/mem/cache/tags/base.cc index 153737300..e18026a21 100644 --- a/src/mem/cache/tags/base_tags.cc +++ b/src/mem/cache/tags/base.cc @@ -34,9 +34,9 @@ * Definitions of BaseTags. */ -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "cpu/smt.hh" //maxThreadsPerCPU #include "sim/sim_exit.hh" diff --git a/src/mem/cache/tags/base_tags.hh b/src/mem/cache/tags/base.hh index b7b0c7ef0..b7b0c7ef0 100644 --- a/src/mem/cache/tags/base_tags.hh +++ b/src/mem/cache/tags/base.hh diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 8cbc79813..cabcf18b4 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -38,10 +38,10 @@ #include <list> -#include "mem/cache/cache_blk.hh" +#include "mem/cache/blk.hh" #include "mem/packet.hh" #include "base/hashmap.hh" -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" /** * A fully associative cache block. diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 20babe6bb..2825599f6 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -39,7 +39,7 @@ #include <math.h> -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "mem/cache/tags/iic.hh" #include "base/intmath.hh" #include "sim/core.hh" // for curTick diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 082b3d15e..c9d080683 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -39,11 +39,11 @@ #include <list> #include <vector> -#include "mem/cache/cache_blk.hh" -#include "mem/cache/tags/repl/repl.hh" +#include "mem/cache/blk.hh" +#include "mem/cache/tags/iic_repl/repl.hh" #include "mem/packet.hh" #include "base/statistics.hh" -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" class BaseCache; // Forward declaration diff --git a/src/mem/cache/miss/SConscript b/src/mem/cache/tags/iic_repl/Repl.py index 376d670cd..4c333e897 100644 --- a/src/mem/cache/miss/SConscript +++ b/src/mem/cache/tags/iic_repl/Repl.py @@ -1,6 +1,4 @@ -# -*- mode:python -*- - -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2005-2008 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -28,7 +26,14 @@ # # Authors: Nathan Binkert -Import('*') +from m5.SimObject import SimObject +from m5.params import * +class Repl(SimObject): + type = 'Repl' + abstract = True -Source('mshr.cc') -Source('mshr_queue.cc') +class GenRepl(Repl): + type = 'GenRepl' + fresh_res = Param.Int("Fresh pool residency time") + num_pools = Param.Int("Number of priority pools") + pool_res = Param.Int("Pool residency time") diff --git a/src/mem/cache/tags/repl/gen.cc b/src/mem/cache/tags/iic_repl/gen.cc index bc4e6b86a..487b227da 100644 --- a/src/mem/cache/tags/repl/gen.cc +++ b/src/mem/cache/tags/iic_repl/gen.cc @@ -38,7 +38,7 @@ #include "base/misc.hh" #include "mem/cache/tags/iic.hh" -#include "mem/cache/tags/repl/gen.hh" +#include "mem/cache/tags/iic_repl/gen.hh" #include "params/GenRepl.hh" #include "sim/host.hh" diff --git a/src/mem/cache/tags/repl/gen.hh b/src/mem/cache/tags/iic_repl/gen.hh index 09a8d5995..22436b384 100644 --- a/src/mem/cache/tags/repl/gen.hh +++ b/src/mem/cache/tags/iic_repl/gen.hh @@ -39,7 +39,7 @@ #include <list> #include "base/statistics.hh" -#include "mem/cache/tags/repl/repl.hh" +#include "mem/cache/tags/iic_repl/repl.hh" #include "params/GenRepl.hh" /** diff --git a/src/mem/cache/tags/repl/repl.hh b/src/mem/cache/tags/iic_repl/repl.hh index cdb5ae4b8..cdb5ae4b8 100644 --- a/src/mem/cache/tags/repl/repl.hh +++ b/src/mem/cache/tags/iic_repl/repl.hh diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 0a8587c20..7f352e9c4 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -35,7 +35,7 @@ #include <string> -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "base/intmath.hh" #include "mem/cache/tags/lru.hh" #include "sim/core.hh" diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index 26038d709..ea5606cde 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -39,10 +39,10 @@ #include <cstring> #include <list> -#include "mem/cache/cache_blk.hh" // base class +#include "mem/cache/blk.hh" // base class #include "mem/packet.hh" // for inlined functions #include <assert.h> -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" class BaseCache; diff --git a/src/mem/cache/tags/split.cc b/src/mem/cache/tags/split.cc index ae284766d..0df85cc92 100644 --- a/src/mem/cache/tags/split.cc +++ b/src/mem/cache/tags/split.cc @@ -41,7 +41,7 @@ #include "base/intmath.hh" #include "base/output.hh" #include "base/trace.hh" -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "mem/cache/tags/split.hh" #include "mem/cache/tags/split_lifo.hh" #include "mem/cache/tags/split_lru.hh" diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh index ab48ce769..e8954f791 100644 --- a/src/mem/cache/tags/split.hh +++ b/src/mem/cache/tags/split.hh @@ -39,11 +39,11 @@ #include <cstring> #include <list> -#include "mem/cache/cache_blk.hh" // base class +#include "mem/cache/blk.hh" // base class #include "mem/cache/tags/split_blk.hh" #include "mem/packet.hh" // for inlined functions #include <assert.h> -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" #include "base/hashmap.hh" class BaseCache; diff --git a/src/mem/cache/tags/split_blk.hh b/src/mem/cache/tags/split_blk.hh index f38516180..d2efe08df 100644 --- a/src/mem/cache/tags/split_blk.hh +++ b/src/mem/cache/tags/split_blk.hh @@ -36,7 +36,7 @@ #ifndef __SPLIT_BLK_HH__ #define __SPLIT_BLK_HH__ -#include "mem/cache/cache_blk.hh" // base class +#include "mem/cache/blk.hh" // base class /** * Split cache block. diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc index 4ee2473a4..3bdc7cae9 100644 --- a/src/mem/cache/tags/split_lifo.cc +++ b/src/mem/cache/tags/split_lifo.cc @@ -35,7 +35,7 @@ #include <string> -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "base/intmath.hh" #include "mem/cache/tags/split_lifo.hh" #include "sim/core.hh" diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh index 13ccf7ef4..0fd5f5c3c 100644 --- a/src/mem/cache/tags/split_lifo.hh +++ b/src/mem/cache/tags/split_lifo.hh @@ -39,12 +39,12 @@ #include <cstring> #include <list> -#include "mem/cache/cache_blk.hh" // base class +#include "mem/cache/blk.hh" // base class #include "mem/cache/tags/split_blk.hh" #include "mem/packet.hh" // for inlined functions #include "base/hashmap.hh" #include <assert.h> -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" class BaseCache; diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc index 4d271a92a..bcccdcb30 100644 --- a/src/mem/cache/tags/split_lru.cc +++ b/src/mem/cache/tags/split_lru.cc @@ -35,7 +35,7 @@ #include <string> -#include "mem/cache/base_cache.hh" +#include "mem/cache/base.hh" #include "base/intmath.hh" #include "mem/cache/tags/split_lru.hh" #include "sim/core.hh" diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh index a708ef740..d41b6efa7 100644 --- a/src/mem/cache/tags/split_lru.hh +++ b/src/mem/cache/tags/split_lru.hh @@ -39,11 +39,11 @@ #include <cstring> #include <list> -#include "mem/cache/cache_blk.hh" // base class +#include "mem/cache/blk.hh" // base class #include "mem/cache/tags/split_blk.hh" #include "mem/packet.hh" // for inlined functions #include <assert.h> -#include "mem/cache/tags/base_tags.hh" +#include "mem/cache/tags/base.hh" class BaseCache; |