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authorLisa Hsu <hsul@eecs.umich.edu>2008-11-04 11:35:42 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2008-11-04 11:35:42 -0500
commitdd99ff23c6a71f7173014b5008d0cf12b7ef223a (patch)
tree01ce6020c898958712699adffe3a1a5a5c9e058d /src/mem/cache
parentd857faf073895dcfde97141bd6346fe5d4317f8e (diff)
downloadgem5-dd99ff23c6a71f7173014b5008d0cf12b7ef223a.tar.xz
get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/base.hh2
-rw-r--r--src/mem/cache/cache_impl.hh20
-rw-r--r--src/mem/cache/mshr_queue.cc2
3 files changed, 12 insertions, 12 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index d97021024..601e9bd48 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -481,7 +481,7 @@ class BaseCache : public MemObject
void incMissCount(PacketPtr pkt)
{
- misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+ misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
if (missCount) {
--missCount;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index abe3f9b5f..45faa84ce 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -296,7 +296,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) {
// OK to satisfy access
- hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+ hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
satisfyCpuSideRequest(pkt, blk);
return true;
}
@@ -325,7 +325,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
blk->status |= BlkDirty;
// nothing else to do; writeback doesn't expect response
assert(!pkt->needsResponse());
- hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+ hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
return true;
}
@@ -467,8 +467,8 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
if (mshr) {
// MSHR hit
//@todo remove hw_pf here
- mshr_hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
- if (mshr->threadNum != 0/*pkt->req->getThreadNum()*/) {
+ mshr_hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
+ if (mshr->threadNum != 0/*pkt->req->threadId()*/) {
mshr->threadNum = -1;
}
mshr->allocateTarget(pkt, time, order++);
@@ -482,7 +482,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
} else {
// no MSHR
- mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+ mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
// always mark as cache fill for now... if we implement
// no-write-allocate or bypass accesses this will have to
// be changed.
@@ -740,10 +740,10 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
PacketList writebacks;
if (pkt->req->isUncacheable()) {
- mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->getThreadNum()*/] +=
+ mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
miss_latency;
} else {
- mshr_miss_latency[stats_cmd_idx][0/*pkt->req->getThreadNum()*/] +=
+ mshr_miss_latency[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
miss_latency;
}
@@ -784,7 +784,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
assert(!target->pkt->req->isUncacheable());
- missLatency[target->pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] +=
+ missLatency[target->pkt->cmdToIndex()][0/*pkt->req->threadId()*/] +=
completion_time - target->recvTime;
} else {
// not a cache fill, just forwarding response
@@ -862,7 +862,7 @@ Cache<TagStore>::writebackBlk(BlkType *blk)
{
assert(blk && blk->isValid() && blk->isDirty());
- writebacks[0/*pkt->req->getThreadNum()*/]++;
+ writebacks[0/*pkt->req->threadId()*/]++;
Request *writebackReq =
new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
@@ -1261,7 +1261,7 @@ Cache<TagStore>::getNextMSHR()
if (pkt) {
// Update statistic on number of prefetches issued
// (hwpf_mshr_misses)
- mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+ mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
// Don't request bus, since we already have it
return allocateMissBuffer(pkt, curTick, false);
}
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 45331c33d..b5c6cc7b8 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -230,7 +230,7 @@ MSHRQueue::squash(int threadNum)
if (mshr->threadNum == threadNum) {
while (mshr->hasTargets()) {
mshr->popTarget();
- assert(0/*target->req->getThreadNum()*/ == threadNum);
+ assert(0/*target->req->threadId()*/ == threadNum);
}
assert(!mshr->hasTargets());
assert(mshr->ntargets==0);