Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

4 files changed, 27 insertions, 187 deletions

diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 65418b68d..4c9592a1b 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -36,13 +36,13 @@
 #include <vector>
 
 // Must be included first to determine which caches we want
+#include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/config/prefetch.hh"
-
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/cache.hh"
 #include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/BaseCache.hh"
 
 // Tag Templates
 #if defined(USE_CACHE_LRU)
@@ -80,100 +80,16 @@
 using namespace std;
 using namespace TheISA;
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-    Param<int> size;
-    Param<int> assoc;
-    Param<int> block_size;
-    Param<int> latency;
-    Param<int> mshrs;
-    Param<int> tgts_per_mshr;
-    Param<int> write_buffers;
-    Param<bool> prioritizeRequests;
-    Param<Addr> trace_addr;
-    Param<int> hash_delay;
-#if defined(USE_CACHE_IIC)
-    SimObjectParam<Repl *> repl;
-#endif
-    Param<int> subblock_size;
-    Param<Counter> max_miss_count;
-    VectorParam<Range<Addr> > addr_range;
-//    SimObjectParam<MemTraceWriter *> mem_trace;
-    Param<bool> split;
-    Param<int> split_size;
-    Param<bool> lifo;
-    Param<bool> two_queue;
-    Param<bool> prefetch_miss;
-    Param<bool> prefetch_access;
-    Param<int> prefetcher_size;
-    Param<bool> prefetch_past_page;
-    Param<bool> prefetch_serial_squash;
-    Param<Tick> prefetch_latency;
-    Param<int> prefetch_degree;
-    Param<string> prefetch_policy;
-    Param<bool> prefetch_cache_check_push;
-    Param<bool> prefetch_use_cpu_id;
-    Param<bool> prefetch_data_accesses_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-    INIT_PARAM(size, "capacity in bytes"),
-    INIT_PARAM(assoc, "associativity"),
-    INIT_PARAM(block_size, "block size in bytes"),
-    INIT_PARAM(latency, "hit latency in CPU cycles"),
-    INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
-    INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
-    INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
-    INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
-                    false),
-    INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
-
-    INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
-#if defined(USE_CACHE_IIC)
-    INIT_PARAM_DFLT(repl, "replacement policy",NULL),
-#endif
-    INIT_PARAM_DFLT(subblock_size,
-                    "Size of subblock in IIC used for compression",
-                    0),
-    INIT_PARAM_DFLT(max_miss_count,
-                    "The number of misses to handle before calling exit",
-                    0),
-    INIT_PARAM_DFLT(addr_range, "The address range in bytes",
-                    vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
-//    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
-    INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
-    INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
-    INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
-    INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
-    INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
-    INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
-    INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
-    INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
-    INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
-    INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
-    INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
-    INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
-    INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
-    INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
-    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
-END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-
 #define BUILD_CACHE(TAGS, tags)                                      \
     do {                                                                \
-        BasePrefetcher *pf;                                           \
-        if (pf_policy == "tagged") {                                    \
+        BasePrefetcher *pf;                                             \
+        if (prefetch_policy == Enums::tagged) {                         \
             BUILD_TAGGED_PREFETCHER(TAGS);                              \
         }                                                               \
-        else if (pf_policy == "stride") {                               \
+        else if (prefetch_policy == Enums::stride) {                    \
             BUILD_STRIDED_PREFETCHER(TAGS);                             \
         }                                                               \
-        else if (pf_policy == "ghb") {                                  \
+        else if (prefetch_policy == Enums::ghb) {                       \
             BUILD_GHB_PREFETCHER(TAGS);                                 \
         }                                                               \
         else {                                                          \
@@ -184,7 +100,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
                                    true,                                \
                                    prefetch_miss);                      \
         Cache<TAGS> *retval =                                        \
-            new Cache<TAGS>(getInstanceName(), params);              \
+            new Cache<TAGS>(name, params);                              \
         return retval;                                                  \
     } while (0)
 
@@ -314,11 +230,10 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 #endif
 
-CREATE_SIM_OBJECT(BaseCache)
+BaseCache *
+BaseCacheParams::create()
 {
-    string name = getInstanceName();
     int numSets = size / (assoc * block_size);
-    string pf_policy = prefetch_policy;
     if (subblock_size == 0) {
         subblock_size = block_size;
     }
@@ -329,24 +244,21 @@ CREATE_SIM_OBJECT(BaseCache)
                                   max_miss_count);
 
     //Warnings about prefetcher policy
-    if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
-        panic("With no prefetcher, you shouldn't prefetch from"
-              " either miss or access stream\n");
+    if (prefetch_policy == Enums::none) {
+        if (prefetch_miss || prefetch_access)
+            panic("With no prefetcher, you shouldn't prefetch from"
+                  " either miss or access stream\n");
     }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
-         pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
-        warn("With this prefetcher you should chose a prefetch"
-             " stream (miss or access)\nNo Prefetching will occur\n");
-    }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
-         pf_policy == "ghb") && prefetch_miss && prefetch_access) {
-        panic("Can't do prefetches from both miss and access"
-              " stream\n");
-    }
-    if (pf_policy != "tagged" && pf_policy != "stride" &&
-        pf_policy != "ghb"    && pf_policy != "none") {
-        panic("Unrecognized form of a prefetcher: %s, try using"
-              "['none','stride','tagged','ghb']\n", pf_policy);
+
+    if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
+        prefetch_policy == Enums::ghb) {
+
+        if (!prefetch_miss && !prefetch_access)
+            warn("With this prefetcher you should chose a prefetch"
+                 " stream (miss or access)\nNo Prefetching will occur\n");
+
+        if (prefetch_miss && prefetch_access)
+            panic("Can't do prefetches from both miss and access stream");
     }
 
 #if defined(USE_CACHE_IIC)
@@ -367,8 +279,3 @@ CREATE_SIM_OBJECT(BaseCache)
     BUILD_CACHES;
     return NULL;
 }
-
-REGISTER_SIM_OBJECT("BaseCache", BaseCache)
-
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 3fcaec4fa..a65c44f22 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -40,4 +40,3 @@ Source('split_lru.cc')
 
 SimObject('Repl.py')
 Source('repl/gen.cc')
-Source('repl/repl.cc')
diff --git a/src/mem/cache/tags/repl/gen.cc b/src/mem/cache/tags/repl/gen.cc
index ec1c2aaf3..7d1566300 100644
--- a/src/mem/cache/tags/repl/gen.cc
+++ b/src/mem/cache/tags/repl/gen.cc
@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "mem/cache/tags/iic.hh"
 #include "mem/cache/tags/repl/gen.hh"
-#include "sim/builder.hh"
+#include "params/GenRepl.hh"
 #include "sim/host.hh"
 
 using namespace std;
@@ -247,31 +247,8 @@ GenRepl::findTagPtr(unsigned long index)
     return false;
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-    Param<int> num_pools;
-    Param<int> fresh_res;
-    Param<int> pool_res;
-
-END_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-    INIT_PARAM(num_pools, "capacity in bytes"),
-    INIT_PARAM(fresh_res, "associativity"),
-    INIT_PARAM(pool_res, "block size in bytes")
-
-END_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-
-CREATE_SIM_OBJECT(GenRepl)
+GenRepl *
+GenReplParams::create()
 {
-    return new GenRepl(getInstanceName(), num_pools, fresh_res, pool_res);
+    return new GenRepl(name, num_pools, fresh_res, pool_res);
 }
-
-REGISTER_SIM_OBJECT("GenRepl", GenRepl)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/tags/repl/repl.cc b/src/mem/cache/tags/repl/repl.cc
deleted file mode 100644
index ce781eb9f..000000000
--- a/src/mem/cache/tags/repl/repl.cc
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- *          Nathan Binkert
- */
-
-/**
- * Definitions of the base replacement class.
- */
-
-#include "sim/param.hh"
-#include "mem/cache/tags/repl/repl.hh"
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Repl", Repl)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS