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authorAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:24 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:24 -0400
commit0ebbf3f9512609c089257158abd14b9366b72b52 (patch)
treef4cf1da2c6b2cb619319fe03653556206916f8c4 /src/mem/cache
parent33e3e370f217badf6f309e601c16f09eb3080f22 (diff)
downloadgem5-0ebbf3f9512609c089257158abd14b9366b72b52.tar.xz
mem: Add missing stats update for uncacheable MSHRs
This patch adds a missing counter update for the uncacheable accesses. By updating this counter we also get a meaningful average latency for uncacheable accesses (previously inf).
Diffstat (limited to 'src/mem/cache')
-rw-r--r--src/mem/cache/cache_impl.hh6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a530001ae..6817db41e 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -701,8 +701,10 @@ Cache::recvTimingReq(PacketPtr pkt)
}
} else {
// no MSHR
- if (!pkt->req->isUncacheable()) {
- assert(pkt->req->masterId() < system->maxMasters());
+ assert(pkt->req->masterId() < system->maxMasters());
+ if (pkt->req->isUncacheable()) {
+ mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
+ } else {
mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
}