mem-cache: Move replacements stat to the base cache class

Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110
Reviewed-on: https://gem5-review.googlesource.com/10426
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

5 files changed, 8 insertions, 11 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 2c7d9fb68..8143acd67 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -758,4 +758,8 @@ BaseCache::regStats()
         overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
     }
 
+    replacements
+        .name(name() + ".replacements")
+        .desc("number of replacements")
+        ;
 }
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index b006d4b64..69c481825 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -453,6 +453,9 @@ class BaseCache : public MemObject
     /** The average overall latency of an MSHR miss. */
     Stats::Formula overallAvgMshrUncacheableLatency;
 
+    /** Number of replacements of valid blocks. */
+    Stats::Scalar replacements;
+
     /**
      * @}
      */
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index b9625beee..73c7e1956 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1827,6 +1827,7 @@ Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
             } else {
                 writebacks.push_back(cleanEvictBlk(blk));
             }
+            replacements++;
         }
     }
 
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 1d6ed4663..75d117e9c 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -48,7 +48,6 @@
 
 #include "mem/cache/tags/base.hh"
 
-#include "cpu/smt.hh" //maxThreadsPerCPU
 #include "mem/cache/base.hh"
 #include "sim/sim_exit.hh"
 
@@ -92,7 +91,6 @@ BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
     // found block might not actually be replaced there if the
     // coherence protocol says it can't be.
     if (blk->isValid()) {
-        replacements[0]++;
         totalRefs += blk->refCount;
         ++sampledRefs;
 
@@ -125,13 +123,6 @@ BaseTags::regStats()
 
     using namespace Stats;
 
-    replacements
-        .init(maxThreadsPerCPU)
-        .name(name() + ".replacements")
-        .desc("number of replacements")
-        .flags(total)
-        ;
-
     tagsInUse
         .name(name() + ".tagsinuse")
         .desc("Cycle average of tags in use")
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 4cf67747b..c04329fe9 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -104,8 +104,6 @@ class BaseTags : public ClockedObject
      * @{
      */
 
-    /** Number of replacements of valid blocks per thread. */
-    Stats::Vector replacements;
     /** Per cycle average of the number of tags that hold valid data. */
     Stats::Average tagsInUse;