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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-10-13 01:57:31 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-10-13 01:57:31 -0700 |
| commit | 930c653270b1523cbeb32a4b48d1fd08eaac6eb8 (patch) | |
| tree | 57a7c91f46975998626424123edada275e8649fb /src/mem/cache | |
| parent | b273e0be33049fc36b386b5ba183f69de53268c2 (diff) | |
| download | gem5-930c653270b1523cbeb32a4b48d1fd08eaac6eb8.tar.xz | |
Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 86bf79b7b..7d19ff7a1 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -306,7 +306,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, int &lat, PacketList &writebacks) { if (pkt->req->isUncacheable()) { - if (pkt->req->isClrex()) { + if (pkt->req->isClearLL()) { tags->clearLocks(); } else { blk = tags->findBlock(pkt->getAddr()); @@ -449,7 +449,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt) } if (pkt->req->isUncacheable()) { - if (pkt->req->isClrex()) { + if (pkt->req->isClearLL()) { tags->clearLocks(); } else { BlkType *blk = tags->findBlock(pkt->getAddr()); |