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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-01 15:21:03 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-17 13:06:23 +0000 |
| commit | 4dd475c1c0db6915f811a246c9e6fce8a61a6a77 (patch) | |
| tree | ff494ce48de95600e3aac7cedc40905edcba2fdf /src/mem/cache | |
| parent | f9b549fbf572ac1b8b40ee86411eb9331a2bf458 (diff) | |
| download | gem5-4dd475c1c0db6915f811a246c9e6fce8a61a6a77.tar.xz | |
arch-arm: Use ExceptionLevel type in TlbEntry
Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The
variable is representing the translation regime it is targeting.
Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/mem/cache')
0 files changed, 0 insertions, 0 deletions