mem: Eliminate the Base(Slave|Master)Port classes.

The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.

Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

2 files changed, 0 insertions, 5 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0de7f2150..bc29c8cee 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -64,9 +64,6 @@
 #include "params/WriteAllocator.hh"
 #include "sim/core.hh"
 
-class BaseMasterPort;
-class BaseSlavePort;
-
 using namespace std;
 
 BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 87948294e..ceb356a1a 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -81,9 +81,7 @@
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"
 
-class BaseMasterPort;
 class BasePrefetcher;
-class BaseSlavePort;
 class MSHR;
 class MasterPort;
 class QueueEntry;