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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:36 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:36 -0400 |
commit | 995e6e4670f52c52f798320055d74994e6539cda (patch) | |
tree | bd758d4a220f06412abe4a7484369b18ae1ea0be /src/mem/coherent_bus.hh | |
parent | 14f9c77dd36fef8ab509bc17ecbe422555daa9c6 (diff) | |
download | gem5-995e6e4670f52c52f798320055d74994e6539cda.tar.xz |
Bus: Add a notion of layers to the buses
This patch moves all flow control, arbitration and state information
into a bus layer. The layer is thus responsible for all the state
transitions, and for keeping hold of the retry list. Consequently the
layer is also responsible for the draining.
With this change, the non-coherent and coherent bus are given a single
layer to avoid changing any temporal behaviour, but the patch opens up
for adding more layers.
Diffstat (limited to 'src/mem/coherent_bus.hh')
-rw-r--r-- | src/mem/coherent_bus.hh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh index 460afd828..b5f0cdee5 100644 --- a/src/mem/coherent_bus.hh +++ b/src/mem/coherent_bus.hh @@ -70,6 +70,11 @@ class CoherentBus : public BaseBus protected: /** + * Declare the single layer of this bus. + */ + Layer layer; + + /** * Declaration of the coherent bus slave port type, one will be * instantiated for each of the master ports connecting to the * bus. @@ -231,6 +236,10 @@ class CoherentBus : public BaseBus snoop response.*/ virtual bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id); + /** Timing function called by port when it is once again able to process + * requests. */ + void recvRetry(); + /** * Forward a timing packet to our snoopers, potentially excluding * one of the connected coherent masters to avoid sending a packet @@ -285,6 +294,8 @@ class CoherentBus : public BaseBus virtual void init(); CoherentBus(const CoherentBusParams *p); + + unsigned int drain(Event *de); }; #endif //__MEM_COHERENT_BUS_HH__ |