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| author | Neha Agarwal <neha.agarwal@arm.com> | 2013-11-01 11:56:25 -0400 |
|---|---|---|
| committer | Neha Agarwal <neha.agarwal@arm.com> | 2013-11-01 11:56:25 -0400 |
| commit | da6fd72f62578d0a981de8bb37dfb803d6c13f8a (patch) | |
| tree | 01f84f28e4e1365fa3232c24a9415a50707ec35b /src/mem/coherent_bus.hh | |
| parent | ee6b41a1e41656b15f9f77bff5effbba27133603 (diff) | |
| download | gem5-da6fd72f62578d0a981de8bb37dfb803d6c13f8a.tar.xz | |
mem: Just-in-time write scheduling in DRAM controller
This patch removes the untimed while loop in the write scheduling
mechanism and now schedule commands taking into account the minimum
timing constraint. It also introduces an optimization to track write
queue size and switch from writes to reads if the number of write
requests fall below write low threshold.
Diffstat (limited to 'src/mem/coherent_bus.hh')
0 files changed, 0 insertions, 0 deletions