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authorAndreas Hansson <andreas.hansson@arm.com>2012-07-09 12:35:37 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-07-09 12:35:37 -0400
commit8caaac048ae49310b905e190b20459232ae7aa9d (patch)
treec46f4657b287505ae3fa89eda6c1bf43c4efc3c2 /src/mem/coherent_bus.hh
parent995e6e4670f52c52f798320055d74994e6539cda (diff)
downloadgem5-8caaac048ae49310b905e190b20459232ae7aa9d.tar.xz
Bus: Split the bus into separate request/response layers
This patch splits the existing buses into multiple layers. The non-coherent bus is split into a request and a response layer, and the coherent bus adds an additional layer for the snoop responses. The layer is modified to be templatised on the port type, such that the different layers can have retryLists with either master or slave ports. This patch also removes the dynamic cast from the retry, as previously promised when moving the recvRetry from the port base class to the master/slave port respectively. Overall, the split bus more closely reflects any modern on-chip bus and should be at step in the right direction. From this point, it would be reasonable straight forward to add separate layers (and thus contention points and arbitration) for each port and thus create a true crossbar. The regressions all produce the correct output, but have varying degrees of changes to their statistics. A separate patch will be pushed with the updates to the reference statistics.
Diffstat (limited to 'src/mem/coherent_bus.hh')
-rw-r--r--src/mem/coherent_bus.hh7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh
index b5f0cdee5..a28b388d5 100644
--- a/src/mem/coherent_bus.hh
+++ b/src/mem/coherent_bus.hh
@@ -70,9 +70,12 @@ class CoherentBus : public BaseBus
protected:
/**
- * Declare the single layer of this bus.
+ * Declare the three layers of this bus, one for requests, one
+ * for responses, and one for snoop responses
*/
- Layer layer;
+ Layer<SlavePort> reqLayer;
+ Layer<MasterPort> respLayer;
+ Layer<SlavePort> snoopRespLayer;
/**
* Declaration of the coherent bus slave port type, one will be