summaryrefslogtreecommitdiff
path: root/src/mem/coherent_bus.hh
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:01 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:01 -0400
commit2308f812ef848d027b99dd52c0900aed11260d87 (patch)
tree8f2dfe7b5345e74eb1b0b3ebb7417a5587ba5395 /src/mem/coherent_bus.hh
parente82996d9dad5ac38fe2c8709c05b26cf92d356e8 (diff)
downloadgem5-2308f812ef848d027b99dd52c0900aed11260d87.tar.xz
mem: Make the buses multi layered
This patch makes the buses multi layered, and effectively creates a crossbar structure with distributed contention ports at the destination ports. Before this patch, a bus could have a single request, response and snoop response in flight at any time, and with these changes there can be as many requests as connected slaves (bus master ports), and as many responses as connected masters (bus slave ports). Together with address interleaving, this patch enables us to create high-throughput memory interconnects, e.g. 50+ GByte/s.
Diffstat (limited to 'src/mem/coherent_bus.hh')
-rw-r--r--src/mem/coherent_bus.hh13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh
index eb8b41e6a..d8ddd507c 100644
--- a/src/mem/coherent_bus.hh
+++ b/src/mem/coherent_bus.hh
@@ -72,12 +72,15 @@ class CoherentBus : public BaseBus
protected:
/**
- * Declare the three layers of this bus, one for requests, one
+ * Declare the layers of this bus, one vector for requests, one
* for responses, and one for snoop responses
*/
- Layer<SlavePort> reqLayer;
- Layer<MasterPort> respLayer;
- Layer<SlavePort> snoopRespLayer;
+ typedef Layer<SlavePort,MasterPort> ReqLayer;
+ typedef Layer<MasterPort,SlavePort> RespLayer;
+ typedef Layer<SlavePort,MasterPort> SnoopLayer;
+ std::vector<ReqLayer*> reqLayers;
+ std::vector<RespLayer*> respLayers;
+ std::vector<SnoopLayer*> snoopLayers;
/**
* Declaration of the coherent bus slave port type, one will be
@@ -309,6 +312,8 @@ class CoherentBus : public BaseBus
CoherentBus(const CoherentBusParams *p);
+ virtual ~CoherentBus();
+
unsigned int drain(DrainManager *dm);
virtual void regStats();