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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:24 -0400 |
| commit | ee6b41a1e41656b15f9f77bff5effbba27133603 (patch) | |
| tree | ae080814212126754b99956b773ef710dbbcd2af /src/mem/coherent_bus.hh | |
| parent | 491d3a77cfe90b21c83304a2d4a5af54c909c916 (diff) | |
| download | gem5-ee6b41a1e41656b15f9f77bff5effbba27133603.tar.xz | |
mem: Add tRRD as a timing parameter for the DRAM controller
This patch adds the tRRD parameter to the DRAM controller. With the
recent addition of the actAllowedAt member for each bank, this
addition is trivial.
Diffstat (limited to 'src/mem/coherent_bus.hh')
0 files changed, 0 insertions, 0 deletions