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authorAndreas Hansson <andreas.hansson@arm.com>2015-11-06 03:26:43 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-11-06 03:26:43 -0500
commit7433d77fcf74ddcd6052a60e0251a1d5d1a46e44 (patch)
tree5e6fec96caf87968ce5e826320794c0d83a5dee5 /src/mem/coherent_xbar.cc
parentafa252b0b962be0192b6badf81d2d39ec4f40e4f (diff)
downloadgem5-7433d77fcf74ddcd6052a60e0251a1d5d1a46e44.tar.xz
mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to allow clean writebacks. This functionality is crucial, especially when having exclusive (victim) caches. For example, if read-only L1 instruction caches are not sending clean writebacks, there will never be any spills from the L1 to the L2. At the moment the cache model defaults to not sending clean writebacks, and this should possibly be re-evaluated. The implementation of clean writebacks relies on a new packet command WritebackClean, which acts much like a Writeback (renamed WritebackDirty), and also much like a CleanEvict. On eviction of a clean block the cache either sends a clean evict, or a clean writeback, and if any copies are still cached upstream the clean evict/writeback is dropped. Similarly, if a clean evict/writeback reaches a cache where there are outstanding MSHRs for the block, the packet is dropped. In the typical case though, the clean writeback allocates a block in the downstream cache, and marks it writable if the evicted block was writable. The patch changes the O3_ARM_v7a L1 cache configuration and the default L1 caches in config/common/Caches.py
Diffstat (limited to 'src/mem/coherent_xbar.cc')
-rw-r--r--src/mem/coherent_xbar.cc16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 8407f5350..b44009a42 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -199,7 +199,7 @@ CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
pkt->cmdString(), pkt->getAddr(), sf_res.first.size(),
sf_res.second);
- if (pkt->evictingBlock()) {
+ if (pkt->isEviction()) {
// for block-evicting packets, i.e. writebacks and
// clean evictions, there is no need to snoop up, as
// all we do is determine if the block is cached or
@@ -220,10 +220,11 @@ CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
}
// forwardTiming snooped into peer caches of the sender, and if
- // this is a clean evict, but the packet is found in a cache, do
- // not forward it
- if (pkt->cmd == MemCmd::CleanEvict && pkt->isBlockCached()) {
- DPRINTF(CoherentXBar, "recvTimingReq: Clean evict 0x%x still cached, "
+ // this is a clean evict or clean writeback, but the packet is
+ // found in a cache, do not forward it
+ if ((pkt->cmd == MemCmd::CleanEvict ||
+ pkt->cmd == MemCmd::WritebackClean) && pkt->isBlockCached()) {
+ DPRINTF(CoherentXBar, "Clean evict/writeback %#llx still cached, "
"not forwarding\n", pkt->getAddr());
// update the layer state and schedule an idle event
@@ -634,8 +635,9 @@ CoherentXBar::recvAtomic(PacketPtr pkt, PortID slave_port_id)
// forwardAtomic snooped into peer caches of the sender, and if
// this is a clean evict, but the packet is found in a cache, do
// not forward it
- if (pkt->cmd == MemCmd::CleanEvict && pkt->isBlockCached()) {
- DPRINTF(CoherentXBar, "recvAtomic: Clean evict 0x%x still cached, "
+ if ((pkt->cmd == MemCmd::CleanEvict ||
+ pkt->cmd == MemCmd::WritebackClean) && pkt->isBlockCached()) {
+ DPRINTF(CoherentXBar, "Clean evict/writeback %#llx still cached, "
"not forwarding\n", pkt->getAddr());
return 0;
}