mem: Add a GDDR5 DRAM config

This patch adds a first cut GDDR5 config to accommodate the users
combining gem5 and GPUSim. The config is based on a SK Hynix
datasheet, and the Nvidia GTX580 specification. Someone from the
GPUSim user-camp should tweak the default page-policy and static
frontend and backend latencies.

1 files changed, 5 insertions, 1 deletions

diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 1beebdd01..8378debf1 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -115,6 +115,9 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
         for (int b = 0; b < banksPerRank; b++) {
             banks[r][b].rank = r;
             banks[r][b].bank = b;
+            // GDDR addressing of banks to BG is linear.
+            // Here we assume that all DRAM generations address bank groups as
+            // follows:
             if (bankGroupArch) {
                 // Simply assign lower bits to bank group in order to
                 // rotate across bank groups as banks are incremented
@@ -224,7 +227,8 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
                   tCCD_L, tBURST, bankGroupsPerRank);
         }
         // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
-        if (tRRD_L <= tRRD) {
+        // some datasheets might specify it equal to tRRD
+        if (tRRD_L < tRRD) {
             fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
                   "bank groups per rank (%d) is greater than 1\n",
                   tRRD_L, tRRD, bankGroupsPerRank);