summaryrefslogtreecommitdiff
path: root/src/mem/dram_ctrl.cc
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2015-11-06 03:26:36 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-11-06 03:26:36 -0500
commit6b70afd0d4ec8821105e506d7a20f9af01b8eafb (patch)
tree401326ebed801c86355d7b97644feb5fce0bc134 /src/mem/dram_ctrl.cc
parent8bc925e36d0e5de7e70a6d5bf2b1824649932599 (diff)
downloadgem5-6b70afd0d4ec8821105e506d7a20f9af01b8eafb.tar.xz
mem: Use the packet delays and do not just zero them out
This patch updates the I/O devices, bridge and simple memory to take the packet header and payload delay into account in their latency calculations. In all cases we add the header delay, i.e. the accumulated pipeline delay of any crossbars, and the payload delay needed for deserialisation of any payload. Due to the additional unknown latency contribution, the packet queue of the simple memory is changed to use insertion sorting based on the time stamp. Moreover, since the memory hands out exclusive (non shared) responses, we also need to ensure ordering for reads to the same address.
Diffstat (limited to 'src/mem/dram_ctrl.cc')
0 files changed, 0 insertions, 0 deletions