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| author | Wendy Elsasser <wendy.elsasser@arm.com> | 2017-02-15 09:28:44 -0600 |
|---|---|---|
| committer | Wendy Elsasser <wendy.elsasser@arm.com> | 2017-02-15 09:28:44 -0600 |
| commit | ddc6931573fa0858df4a42223afa95a60dcf8ea3 (patch) | |
| tree | 3d2aaf65ed577c41d10a38baa9ea56727aaa0ac1 /src/mem/dram_ctrl.cc | |
| parent | 4b8b9c0585205f82cc8bba268dc54cd2e2af8f75 (diff) | |
| download | gem5-ddc6931573fa0858df4a42223afa95a60dcf8ea3.tar.xz | |
mem: fix assertion in respondEvent
Assertion in the respondEvent erroneously fired.
The assertion verifies that the controller has not moved to a low-power
state prior to receiving read data from the memory.
The original assertion triggered if the state was not:
PWR_IDLE or PWR_ACT.
In the case that failed, a periodic refresh event occurred around the
read. The REF is stalled until the final read burst is issued
and the subsequent PRE closes the bank. While the PRE will temporarily
move the state to PWR_IDLE, state will immediately transition to PWR_REF
due to the pending refresh operation. This state does not match the
assertion, which is subsequently triggered.
Fixed the assertion by explicitly checking that the state is not a low
power state
!PWR_SREF && !PWR_PRE_PDN && !PWR_ACT_PDN
Change-Id: I82921a733bbeac2bcb5a487c2f981448d41ed50b
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Diffstat (limited to 'src/mem/dram_ctrl.cc')
| -rw-r--r-- | src/mem/dram_ctrl.cc | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index ada70279f..4398611e5 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2016 ARM Limited + * Copyright (c) 2010-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -678,18 +678,20 @@ DRAMCtrl::processRespondEvent() // read response received, decrement count --dram_pkt->rankRef.outstandingEvents; - // at this moment should be either ACT or IDLE depending on - // if PRE has occurred to close all banks - assert((dram_pkt->rankRef.pwrState == PWR_ACT) || - (dram_pkt->rankRef.pwrState == PWR_IDLE)); + // at this moment should not have transitioned to a low-power state + assert((dram_pkt->rankRef.pwrState != PWR_SREF) && + (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) && + (dram_pkt->rankRef.pwrState != PWR_ACT_PDN)); // track if this is the last packet before idling // and that there are no outstanding commands to this rank - if (dram_pkt->rankRef.lowPowerEntryReady()) { + // if REF in progress, transition to LP state should not occur + // until REF completes + if ((dram_pkt->rankRef.refreshState == REF_IDLE) && + (dram_pkt->rankRef.lowPowerEntryReady())) { // verify that there are no events scheduled assert(!dram_pkt->rankRef.activateEvent.scheduled()); assert(!dram_pkt->rankRef.prechargeEvent.scheduled()); - assert(dram_pkt->rankRef.refreshState == REF_IDLE); // if coming from active state, schedule power event to // active power-down else go to precharge power-down |