diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:19 -0800 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:19 -0800 |
commit | 5592798865ece858bab2b444bc782d19121e2566 (patch) | |
tree | 80803048c903c424ed9f1200b5dc1a29ed3ff6b8 /src/mem/dram_ctrl.cc | |
parent | dc8018a5c3482008232e6faaa2d96cf20aed7485 (diff) | |
download | gem5-5592798865ece858bab2b444bc782d19121e2566.tar.xz |
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
Diffstat (limited to 'src/mem/dram_ctrl.cc')
-rw-r--r-- | src/mem/dram_ctrl.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index e3c532455..c7ad3b448 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -723,7 +723,7 @@ DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) if (memSchedPolicy == Enums::fcfs) { // check if there is a packet going to a free rank - for(auto i = queue.begin(); i != queue.end() ; ++i) { + for (auto i = queue.begin(); i != queue.end() ; ++i) { DRAMPacket* dram_pkt = *i; if (ranks[dram_pkt->rank]->isAvailable()) { queue.erase(i); @@ -911,7 +911,7 @@ DRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); // start by enforcing tRRD - for(int i = 0; i < banksPerRank; i++) { + for (int i = 0; i < banksPerRank; i++) { // next activate to any bank in this rank must not happen // before tRRD if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { @@ -956,7 +956,7 @@ DRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " "no earlier than %llu\n", activationLimit, rank_ref.actTicks.back() + tXAW); - for(int j = 0; j < banksPerRank; j++) + for (int j = 0; j < banksPerRank; j++) // next activate must not happen before end of window rank_ref.banks[j].actAllowedAt = std::max(rank_ref.actTicks.back() + tXAW, @@ -1073,8 +1073,8 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) // update the time for the next read/write burst for each // bank (add a max with tCCD/tCCD_L here) Tick cmd_dly; - for(int j = 0; j < ranksPerChannel; j++) { - for(int i = 0; i < banksPerRank; i++) { + for (int j = 0; j < ranksPerChannel; j++) { + for (int i = 0; i < banksPerRank; i++) { // next burst to same bank group in this rank must not happen // before tCCD_L. Different bank group timing requirement is // tBURST; Add tCS for different ranks @@ -1454,7 +1454,7 @@ DRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, // bank in question vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); for (const auto& p : queue) { - if(p->rankRef.isAvailable()) + if (p->rankRef.isAvailable()) got_waiting[p->bankId] = true; } |