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author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:26 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:26 -0500 |
commit | baf88e908d285191c13b5e96c16065957e5af7a6 (patch) | |
tree | 7361d43b795f80a80a89995eb6865d51a972f36a /src/mem/dram_ctrl.cc | |
parent | 3a5c975fd7a0e6c8f25067c1794581056c01c22c (diff) | |
download | gem5-baf88e908d285191c13b5e96c16065957e5af7a6.tar.xz |
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
Diffstat (limited to 'src/mem/dram_ctrl.cc')
0 files changed, 0 insertions, 0 deletions