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authorAndreas Hansson <andreas.hansson@arm.com>2014-06-30 13:56:02 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-06-30 13:56:02 -0400
commitb4ce51eb9ecfb053e2aacbabba318a41890f436e (patch)
treecaf12feccc4b3ba68347d20c2a1feab7bd4e477c /src/mem/dram_ctrl.cc
parentd59bc8ee1fbfe26567e3dfb038c60b52f4e20946 (diff)
downloadgem5-b4ce51eb9ecfb053e2aacbabba318a41890f436e.tar.xz
mem: Add bank and rank indices as fields to the DRAM bank
This patch adds the index of the bank and rank as a field so that we can determine the identity of a given bank (reference or pointer) for the power tracing. We also grab the opportunity of cleaning up the arguments used for identifying the bank when activating.
Diffstat (limited to 'src/mem/dram_ctrl.cc')
-rw-r--r--src/mem/dram_ctrl.cc30
1 files changed, 19 insertions, 11 deletions
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index e4248b337..b4e1eac7b 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -96,6 +96,14 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
actTicks[c].resize(activationLimit, 0);
}
+ // set the bank indices
+ for (int r = 0; r < ranksPerChannel; r++) {
+ for (int b = 0; b < banksPerRank; b++) {
+ banks[r][b].rank = r;
+ banks[r][b].bank = b;
+ }
+ }
+
// perform a basic check of the write thresholds
if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
fatal("Write buffer low threshold %d must be smaller than the "
@@ -752,23 +760,24 @@ DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
}
void
-DRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank,
- uint32_t row, Bank& bank_ref)
+DRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row)
{
- assert(0 <= rank && rank < ranksPerChannel);
+ // get the rank index from the bank
+ uint8_t rank = bank.rank;
+
assert(actTicks[rank].size() == activationLimit);
DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
// update the open row
- assert(bank_ref.openRow == Bank::NO_ROW);
- bank_ref.openRow = row;
+ assert(bank.openRow == Bank::NO_ROW);
+ bank.openRow = row;
// start counting anew, this covers both the case when we
// auto-precharged, and when this access is forced to
// precharge
- bank_ref.bytesAccessed = 0;
- bank_ref.rowAccesses = 0;
+ bank.bytesAccessed = 0;
+ bank.rowAccesses = 0;
++numBanksActive;
assert(numBanksActive <= banksPerRank * ranksPerChannel);
@@ -777,10 +786,10 @@ DRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank,
act_tick, numBanksActive);
// The next access has to respect tRAS for this bank
- bank_ref.preAllowedAt = act_tick + tRAS;
+ bank.preAllowedAt = act_tick + tRAS;
// Respect the row-to-column command delay
- bank_ref.colAllowedAt = act_tick + tRCD;
+ bank.colAllowedAt = act_tick + tRCD;
// start by enforcing tRRD
for(int i = 0; i < banksPerRank; i++) {
@@ -922,8 +931,7 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
// Record the activation and deal with all the global timing
// constraints caused be a new activation (tRRD and tXAW)
- activateBank(act_tick, dram_pkt->rank, dram_pkt->bank,
- dram_pkt->row, bank);
+ activateBank(bank, act_tick, dram_pkt->row);
// issue the command as early as possible
cmd_at = bank.colAllowedAt;