mem: Ensure DRAM controller is idle when in atomic mode

This patch addresses an issue seen with the KVM CPU where the refresh
events scheduled by the DRAM controller forces the simulator to switch
out of the KVM mode, thus killing performance.

The current patch works around the fact that we currently have no
proper API to inform a SimObject of the mode switches. Instead we rely
on drainResume being called after any switch, and cache the previous
mode locally to be able to decide on appropriate actions.

The switcheroo regression require a minor stats bump as a result.

1 files changed, 13 insertions, 2 deletions

diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index ade717695..3aa06feac 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -121,6 +121,11 @@ class DRAMCtrl : public AbstractMemory
     MemoryPort port;
 
     /**
+     * Remeber if the memory system is in timing mode
+     */
+    bool isTimingMode;
+
+    /**
      * Remember if we have to retry a request when available.
      */
     bool retryRdReq;
@@ -340,6 +345,11 @@ class DRAMCtrl : public AbstractMemory
         void startup(Tick ref_tick);
 
         /**
+         * Stop the refresh events.
+         */
+        void suspend();
+
+        /**
          * Check if the current rank is available for scheduling.
          *
          * @param Return true if the rank is idle from a refresh point of view
@@ -855,8 +865,9 @@ class DRAMCtrl : public AbstractMemory
     virtual BaseSlavePort& getSlavePort(const std::string& if_name,
                                         PortID idx = InvalidPortID);
 
-    virtual void init();
-    virtual void startup();
+    virtual void init() M5_ATTR_OVERRIDE;
+    virtual void startup() M5_ATTR_OVERRIDE;
+    virtual void drainResume() M5_ATTR_OVERRIDE;
 
   protected: