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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
| commit | 6753cb705e726becc433ee39238ca00a5b929fe4 (patch) | |
| tree | 4ab982c9b737ef99a54d196f5d653030272189f6 /src/mem/dram_ctrl.hh | |
| parent | 60799dc5523e3a2174d7bf6a4f3e913e938b6163 (diff) | |
| download | gem5-6753cb705e726becc433ee39238ca00a5b929fe4.tar.xz | |
mem: Add tRTP to the DRAM controller
This patch adds the tRTP timing constraint, governing the minimum time
between a read command and a precharge. Default values are provided
for the existing DRAM types.
Diffstat (limited to 'src/mem/dram_ctrl.hh')
| -rw-r--r-- | src/mem/dram_ctrl.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index c3ce9dc97..ae55a2d13 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -486,6 +486,7 @@ class DRAMCtrl : public AbstractMemory const Tick tRP; const Tick tRAS; const Tick tWR; + const Tick tRTP; const Tick tRFC; const Tick tREFI; const Tick tRRD; |