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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
| commit | f84ee031ccdb63d016c6f55b578085a2e5af4a4b (patch) | |
| tree | 3c494751302b00722e189fc9e9a2aabd76dfb492 /src/mem/dram_ctrl.hh | |
| parent | 986214f1816be2dc6f3758c4b80d8fbc945495b0 (diff) | |
| download | gem5-f84ee031ccdb63d016c6f55b578085a2e5af4a4b.tar.xz | |
mem: Align cache behaviour in atomic when upstream is responding
Adopt the same flow as in timing mode, where the caches on the path to
memory get to keep the line (if present), and we use the
responderHadWritable flag to determine if we need to forward the
(invalidating) packet or not.
Diffstat (limited to 'src/mem/dram_ctrl.hh')
0 files changed, 0 insertions, 0 deletions