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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-08-26 10:12:45 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-08-26 10:12:45 -0400 |
commit | 56b7796e0d46f6296633b18e0eede042ab7cebc6 (patch) | |
tree | 37e902186f419fa6b6c3c5c2e1846a99d26ff579 /src/mem/dram_ctrl.hh | |
parent | 04d1f61ae8f2a40cfe61aaf0c0271b212da0c314 (diff) | |
download | gem5-56b7796e0d46f6296633b18e0eede042ab7cebc6.tar.xz |
mem: Fix address interleaving bug in DRAM controller
This patch fixes a bug in the DRAM controller address decoding. In
cases where the DRAM burst size (e.g. 32 bytes in a rank with a single
LPDDR3 x32) was smaller than the channel interleaving size
(e.g. systems with a 64-byte cache line) one address bit effectively
got used as a channel bit when it should have been a low-order column
bit.
This patch adds a notion of "columns per stripe", and more clearly
deals with the low-order column bits and high-order column bits. The
patch also relaxes the granularity check such that it is possible to
use interleaving granularities other than the cache line size.
The patch also adds a missing M5_CLASS_VAR_USED to the tCK member as
it is only used in the debug build for now.
Diffstat (limited to 'src/mem/dram_ctrl.hh')
-rw-r--r-- | src/mem/dram_ctrl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index 720383542..fc1a6115b 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -453,6 +453,7 @@ class DRAMCtrl : public AbstractMemory const uint32_t burstSize; const uint32_t rowBufferSize; const uint32_t columnsPerRowBuffer; + const uint32_t columnsPerStripe; const uint32_t ranksPerChannel; const uint32_t banksPerRank; const uint32_t channels; @@ -469,7 +470,7 @@ class DRAMCtrl : public AbstractMemory * Basic memory timing parameters initialized based on parameter * values. */ - const Tick tCK; + const Tick M5_CLASS_VAR_USED tCK; const Tick tWTR; const Tick tRTW; const Tick tBURST; |