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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:14 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:14 -0400 |
commit | a00383a40aeb8347af7e05f3966ab141484921a5 (patch) | |
tree | 606791537a5ecb3b8f349ca65cfd57bce9077327 /src/mem/dram_ctrl.hh | |
parent | 7c18691db1bc450b04142502e5c324ad612318ab (diff) | |
download | gem5-a00383a40aeb8347af7e05f3966ab141484921a5.tar.xz |
mem: Track DRAM read/write switching and add hysteresis
This patch adds stats for tracking the number of reads/writes per bus
turn around, and also adds hysteresis to the write-to-read switching
to ensure that the queue does not oscilate around the low threshold.
Diffstat (limited to 'src/mem/dram_ctrl.hh')
-rw-r--r-- | src/mem/dram_ctrl.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index e327f0796..749296634 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -488,6 +488,7 @@ class DRAMCtrl : public AbstractMemory const uint32_t writeLowThreshold; const uint32_t minWritesPerSwitch; uint32_t writesThisTime; + uint32_t readsThisTime; /** * Basic memory timing parameters initialized based on parameter @@ -569,6 +570,8 @@ class DRAMCtrl : public AbstractMemory Stats::Vector rdQLenPdf; Stats::Vector wrQLenPdf; Stats::Histogram bytesPerActivate; + Stats::Histogram rdPerTurnAround; + Stats::Histogram wrPerTurnAround; // Latencies summed over all requests Stats::Scalar totQLat; |