mem: Track DRAM read/write switching and add hysteresis

This patch adds stats for tracking the number of reads/writes per bus
turn around, and also adds hysteresis to the write-to-read switching
to ensure that the queue does not oscilate around the low threshold.

1 files changed, 3 insertions, 0 deletions

diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index e327f0796..749296634 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -488,6 +488,7 @@ class DRAMCtrl : public AbstractMemory
     const uint32_t writeLowThreshold;
     const uint32_t minWritesPerSwitch;
     uint32_t writesThisTime;
+    uint32_t readsThisTime;
 
     /**
      * Basic memory timing parameters initialized based on parameter
@@ -569,6 +570,8 @@ class DRAMCtrl : public AbstractMemory
     Stats::Vector rdQLenPdf;
     Stats::Vector wrQLenPdf;
     Stats::Histogram bytesPerActivate;
+    Stats::Histogram rdPerTurnAround;
+    Stats::Histogram wrPerTurnAround;
 
     // Latencies summed over all requests
     Stats::Scalar totQLat;