mem: Modify drain to ensure banks and power are idled

Add constraint that all ranks have to be in PWR_IDLE
before signaling drain complete

This will ensure that the banks are all closed and the rank
has exited any low-power states.

On suspend, update the power stats to sync the DRAM power logic

The logic maintains the location of the signalDrainDone
method, which is still triggered from either:
1) Read response event
2) Next request event

This ensures that the drain will complete in the READ bus
state and minimizes the changes required.

Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>

1 files changed, 20 insertions, 0 deletions

diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 70b737652..79a68af4b 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -382,6 +382,15 @@ class DRAMCtrl : public AbstractMemory
         bool isAvailable() const { return refreshState == REF_IDLE; }
 
         /**
+         * Check if the current rank has all banks closed and is not
+         * in a low power state
+         *
+         * @param Return true if the rank is idle from a bank
+         *        and power point of view
+         */
+        bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
+
+        /**
          * Let the rank check if it was waiting for requests to drain
          * to allow it to transition states.
          */
@@ -913,6 +922,17 @@ class DRAMCtrl : public AbstractMemory
     virtual void startup() override;
     virtual void drainResume() override;
 
+    /**
+     * Return true once refresh is complete for all ranks and there are no
+     * additional commands enqueued.  (only evaluated when draining)
+     * This will ensure that all banks are closed, power state is IDLE, and
+     * power stats have been updated
+     *
+     * @return true if all ranks have refreshed, with no commands enqueued
+     *
+     */
+    bool allRanksDrained() const;
+
   protected:
 
     Tick recvAtomic(PacketPtr pkt);