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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
| commit | 8c56efe74799b8495ad4dbee061ac62ddbf534d4 (patch) | |
| tree | 5b56f8c9dfab23df0fdebbc31d5251fd5e4a6297 /src/mem/dram_ctrl.hh | |
| parent | 8e3869411d85ddfec1d30a5da4dbfb30adf3e6ea (diff) | |
| download | gem5-8c56efe74799b8495ad4dbee061ac62ddbf534d4.tar.xz | |
mem: Simplify DRAM response scheduling
This patch simplifies the DRAM response scheduling based on the
assumption that they are always returned in order.
Diffstat (limited to 'src/mem/dram_ctrl.hh')
| -rw-r--r-- | src/mem/dram_ctrl.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index c673e0595..24f9729c5 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -367,14 +367,6 @@ class DRAMCtrl : public AbstractMemory void chooseNext(std::deque<DRAMPacket*>& queue); /** - * Move the request at the head of the read queue to the response - * queue, sorting by readyTime.\ If it is the only packet in the - * response queue, schedule a respond event to send it back to the - * outside world - */ - void moveToRespQ(); - - /** * For FR-FCFS policy reorder the read/write queue depending on row buffer * hits and earliest banks available in DRAM */ |