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| author | Marco Balboni <Marco.Balboni@ARM.com> | 2015-03-02 04:00:48 -0500 |
|---|---|---|
| committer | Marco Balboni <Marco.Balboni@ARM.com> | 2015-03-02 04:00:48 -0500 |
| commit | d4ef8368aa1dfb5e1e1ebe155c0fce1070046f83 (patch) | |
| tree | cedda2d21dbee8ba4ef40d828898d3430ea5df9b /src/mem/dramsim2.cc | |
| parent | 36dc93a5fa09765b9d2bac402bb557d228effcad (diff) | |
| download | gem5-d4ef8368aa1dfb5e1e1ebe155c0fce1070046f83.tar.xz | |
mem: Downstream components consumes new crossbar delays
This patch makes the caches and memory controllers consume the delay
that is annotated to a packet by the crossbar. Previously many
components simply threw these delays away. Note that the devices still
do not pay for these delays.
Diffstat (limited to 'src/mem/dramsim2.cc')
| -rw-r--r-- | src/mem/dramsim2.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc index 7346a4515..be244bd4a 100644 --- a/src/mem/dramsim2.cc +++ b/src/mem/dramsim2.cc @@ -268,8 +268,10 @@ DRAMSim2::accessAndRespond(PacketPtr pkt) if (needsResponse) { // access already turned the packet into a response assert(pkt->isResponse()); - - // @todo someone should pay for this + // Here we pay for xbar additional delay and to process the payload + // of the packet. + Tick time = curTick() + pkt->headerDelay + pkt->payloadDelay; + // Reset the timings of the packet pkt->headerDelay = pkt->payloadDelay = 0; DPRINTF(DRAMSim2, "Queuing response for address %lld\n", @@ -281,7 +283,7 @@ DRAMSim2::accessAndRespond(PacketPtr pkt) // if we are not already waiting for a retry, or are scheduled // to send a response, schedule an event if (!retryResp && !sendResponseEvent.scheduled()) - schedule(sendResponseEvent, curTick()); + schedule(sendResponseEvent, time); } else { // @todo the packet is going to be deleted, and the DRAMPacket // is still having a pointer to it |