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author | Marco Balboni <Marco.Balboni@ARM.com> | 2015-02-11 10:23:36 -0500 |
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committer | Marco Balboni <Marco.Balboni@ARM.com> | 2015-02-11 10:23:36 -0500 |
commit | e2828587b3f28c4f37f0fe598209290bc3d41de0 (patch) | |
tree | d0d967c233c0da3d07f045806d6c48e9b6b06190 /src/mem/dramsim2.cc | |
parent | 5a573762d0b27eb26a572581611df2196656641f (diff) | |
download | gem5-e2828587b3f28c4f37f0fe598209290bc3d41de0.tar.xz |
mem: Clarify usage of latency in the cache
This patch adds some much-needed clarity in the specification of the
cache timing. For now, hit_latency and response_latency are kept as
top-level parameters, but the cache itself has a number of local
variables to better map the individual timing variables to different
behaviours (and sub-components).
The introduced variables are:
- lookupLatency: latency of tag lookup, occuring on any access
- forwardLatency: latency that occurs in case of outbound miss
- fillLatency: latency to fill a cache block
We keep the existing responseLatency
The forwardLatency is used by allocateInternalBuffer() for:
- MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
- MSHR allocateMissBuffer (cacheable miss in MSHR queue);
- MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR
queue)
It is our assumption that the time for the above three buffers is the
same. Similarly, for snoop responses passing through the cache we use
forwardLatency.
Diffstat (limited to 'src/mem/dramsim2.cc')
0 files changed, 0 insertions, 0 deletions