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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-08-26 10:14:38 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-08-26 10:14:38 -0400 |
| commit | 9e4cd5bf1ec71023b786b3a779ed4f3ea29ac214 (patch) | |
| tree | d1bbf36638c9c57363bbfdad93c7a541988e66d1 /src/mem/dramsim2.hh | |
| parent | 6fa8015b7fd50e75e97a175a511958b652eca11e (diff) | |
| download | gem5-9e4cd5bf1ec71023b786b3a779ed4f3ea29ac214.tar.xz | |
mem: Fix DRAMSim2 cycle check when restoring from checkpoint
This patch ensures the cycle check is still valid even restoring from
a checkpoint. In this case the DRAMSim2 cycle count is relative to the
startTick rather than 0.
Diffstat (limited to 'src/mem/dramsim2.hh')
| -rw-r--r-- | src/mem/dramsim2.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh index c61b84cbe..7153f3f84 100644 --- a/src/mem/dramsim2.hh +++ b/src/mem/dramsim2.hh @@ -104,6 +104,11 @@ class DRAMSim2 : public AbstractMemory bool retryResp; /** + * Keep track of when the wrapper is started. + */ + Tick startTick; + + /** * Keep track of what packets are outstanding per * address, and do so separately for reads and writes. This is * done so that we can return the right packet on completion from |