summaryrefslogtreecommitdiff
path: root/src/mem/dramsim2.hh
diff options
context:
space:
mode:
authorGabe Black <gabeblack@google.com>2019-03-07 03:02:35 -0800
committerGabe Black <gabeblack@google.com>2019-03-19 10:22:50 +0000
commitd3d24835bcc03ecf312ac6ba7df114656770730f (patch)
tree43bb564a7bc3e22ffd7b1b906f6f96742ecb619a /src/mem/dramsim2.hh
parent378d9ccbeb4053aeeab002159b26625854af54f7 (diff)
downloadgem5-d3d24835bcc03ecf312ac6ba7df114656770730f.tar.xz
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/mem/dramsim2.hh')
-rw-r--r--src/mem/dramsim2.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 6444f75d6..2fd140bb4 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -191,8 +191,8 @@ class DRAMSim2 : public AbstractMemory
DrainState drain() override;
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void init() override;
void startup() override;