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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-06-27 09:35:11 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-06-28 12:48:54 +0000 |
| commit | f6dd997ef43f52f80f5cdb43cd32614ce4169960 (patch) | |
| tree | 1eb4b637b996a72883956fc91fe99a9fd372ccd7 /src/mem/mem_delay.hh | |
| parent | a77222f8d0b09497c8ce6a085c81f3960da9d5f4 (diff) | |
| download | gem5-f6dd997ef43f52f80f5cdb43cd32614ce4169960.tar.xz | |
arch-arm: Fix incorrect t{0,1}sz field in TTBCR
The t0sz and t1sz fields in TTBCR only are only three bits wide unlike
aarch64 which has a 6-bit wide field. The higher bits of the
aarch64-equivalent should be treated as RES0.
Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11589
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/mem/mem_delay.hh')
0 files changed, 0 insertions, 0 deletions