summaryrefslogtreecommitdiff
path: root/src/mem/mem_object.hh
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:12:35 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:12:35 -0400
commit2a740aa09682c32eb8f1f8880f279c943d8c6ee1 (patch)
tree61ca1dcb9336bc1f4dbc791c876875c1c260ca8d /src/mem/mem_object.hh
parent9baa35ba802f2cfb9fb9ecdebf111f4cd793a428 (diff)
downloadgem5-2a740aa09682c32eb8f1f8880f279c943d8c6ee1.tar.xz
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
Diffstat (limited to 'src/mem/mem_object.hh')
-rw-r--r--src/mem/mem_object.hh16
1 files changed, 10 insertions, 6 deletions
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
index 6cc0c4fd3..e12b30661 100644
--- a/src/mem/mem_object.hh
+++ b/src/mem/mem_object.hh
@@ -67,26 +67,30 @@ class MemObject : public ClockedObject
MemObject(const Params *params);
/**
- * Get a master port with a given name and index.
+ * Get a master port with a given name and index. This is used at
+ * binding time and returns a reference to a protocol-agnostic
+ * base master port.
*
* @param if_name Port name
* @param idx Index in the case of a VectorPort
*
* @return A reference to the given port
*/
- virtual MasterPort& getMasterPort(const std::string& if_name,
- int idx = -1);
+ virtual BaseMasterPort& getMasterPort(const std::string& if_name,
+ PortID idx = InvalidPortID);
/**
- * Get a slave port with a given name and index.
+ * Get a slave port with a given name and index. This is used at
+ * binding time and returns a reference to a protocol-agnostic
+ * base master port.
*
* @param if_name Port name
* @param idx Index in the case of a VectorPort
*
* @return A reference to the given port
*/
- virtual SlavePort& getSlavePort(const std::string& if_name,
- int idx = -1);
+ virtual BaseSlavePort& getSlavePort(const std::string& if_name,
+ PortID idx = InvalidPortID);
};
#endif //__MEM_MEM_OBJECT_HH__