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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-03 07:42:21 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-03 07:42:21 -0400
commite1ac9629398027186ef4c2a66772aeff2b4c6792 (patch)
tree69a2591a576690aeafca28eef2374b20b76d7c3c /src/mem/multi_level_page_table_impl.hh
parent23c85407562c3e2e2f3e1ca8b8dcbdc38fac82df (diff)
downloadgem5-e1ac9629398027186ef4c2a66772aeff2b4c6792.tar.xz
arch: Cleanup unused ISA traits constants
This patch prunes unused values, and also unifies how the values are defined (not using an enum for ALPHA), aligning the use of int vs Addr etc. The patch also removes the duplication of PageBytes/PageShift and VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical values and the latter has been removed.
Diffstat (limited to 'src/mem/multi_level_page_table_impl.hh')
-rw-r--r--src/mem/multi_level_page_table_impl.hh24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh
index d944ff04b..9ffcf02e8 100644
--- a/src/mem/multi_level_page_table_impl.hh
+++ b/src/mem/multi_level_page_table_impl.hh
@@ -74,13 +74,13 @@ MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc)
/* setting first level of the page table */
uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
logLevelSize[numLevels-1];
- assert(log_req_size >= LogVMPageSize);
- uint64_t npages = 1 << (log_req_size - LogVMPageSize);
+ assert(log_req_size >= PageShift);
+ uint64_t npages = 1 << (log_req_size - PageShift);
Addr paddr = system->allocPhysPages(npages);
PortProxy &p = system->physProxy;
- p.memsetBlob(paddr, 0, npages << LogVMPageSize);
+ p.memsetBlob(paddr, 0, npages << PageShift);
}
@@ -93,7 +93,7 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
Addr level_base = basePtr;
for (int i = numLevels - 1; i > 0; i--) {
- Addr entry_addr = (level_base<<LogVMPageSize) +
+ Addr entry_addr = (level_base<<PageShift) +
offsets[i] * sizeof(PageTableEntry);
PortProxy &p = system->physProxy;
@@ -106,16 +106,16 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
logLevelSize[i-1];
- assert(log_req_size >= LogVMPageSize);
- uint64_t npages = 1 << (log_req_size - LogVMPageSize);
+ assert(log_req_size >= PageShift);
+ uint64_t npages = 1 << (log_req_size - PageShift);
DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n", npages, i-1);
/* allocate new entry */
Addr next_entry_paddr = system->allocPhysPages(npages);
- p.memsetBlob(next_entry_paddr, 0, npages << LogVMPageSize);
+ p.memsetBlob(next_entry_paddr, 0, npages << PageShift);
- next_entry_pnum = next_entry_paddr >> LogVMPageSize;
+ next_entry_pnum = next_entry_paddr >> PageShift;
pTableISAOps.setPnum(entry, next_entry_pnum);
pTableISAOps.setPTEFields(entry);
p.write<PageTableEntry>(entry_addr, entry);
@@ -125,7 +125,7 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
level_base = next_entry_pnum;
}
- PTE_addr = (level_base<<LogVMPageSize) +
+ PTE_addr = (level_base<<PageShift) +
offsets[0] * sizeof(PageTableEntry);
DPRINTF(MMU, "Returning PTE_addr: %x\n", PTE_addr);
return true;
@@ -148,7 +148,7 @@ MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr, int64_t size, bool clob
PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
Addr entry_paddr = pTableISAOps.getPnum(PTE);
if (!clobber && entry_paddr == 0) {
- pTableISAOps.setPnum(PTE, paddr >> LogVMPageSize);
+ pTableISAOps.setPnum(PTE, paddr >> PageShift);
pTableISAOps.setPTEFields(PTE);
p.write<PageTableEntry>(PTE_addr, PTE);
DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
@@ -193,7 +193,7 @@ MultiLevelPageTable<ISAOps>::remap(Addr vaddr, int64_t size, Addr new_vaddr)
walk(new_vaddr, true, new_PTE_addr);
PageTableEntry new_PTE = p.read<PageTableEntry>(new_PTE_addr);
- pTableISAOps.setPnum(new_PTE, paddr>>LogVMPageSize);
+ pTableISAOps.setPnum(new_PTE, paddr>>PageShift);
pTableISAOps.setPTEFields(new_PTE);
p.write<PageTableEntry>(new_PTE_addr, new_PTE);
DPRINTF(MMU, "Remapping: %#x-%#x\n", vaddr, new_PTE_addr);
@@ -285,7 +285,7 @@ MultiLevelPageTable<ISAOps>::lookup(Addr vaddr, TlbEntry &entry)
if (pnum == 0)
return false;
- entry = TlbEntry(pid, vaddr, pnum << LogVMPageSize);
+ entry = TlbEntry(pid, vaddr, pnum << PageShift);
updateCache(page_addr, entry);
} else {
return false;