mem: Make the buses multi layered

This patch makes the buses multi layered, and effectively creates a
crossbar structure with distributed contention ports at the
destination ports. Before this patch, a bus could have a single
request, response and snoop response in flight at any time, and with
these changes there can be as many requests as connected slaves (bus
master ports), and as many responses as connected masters (bus slave
ports).

Together with address interleaving, this patch enables us to create
high-throughput memory interconnects, e.g. 50+ GByte/s.

1 files changed, 7 insertions, 3 deletions

diff --git a/src/mem/noncoherent_bus.hh b/src/mem/noncoherent_bus.hh
index 8fc2c40d5..e2148c60e 100644
--- a/src/mem/noncoherent_bus.hh
+++ b/src/mem/noncoherent_bus.hh
@@ -73,11 +73,13 @@ class NoncoherentBus : public BaseBus
   protected:
 
     /**
-     * Declare the two layers of this bus, one for requests and one
+     * Declare the layers of this bus, one vector for requests and one
      * for responses.
      */
-    Layer<SlavePort> reqLayer;
-    Layer<MasterPort> respLayer;
+    typedef Layer<SlavePort,MasterPort> ReqLayer;
+    typedef Layer<MasterPort,SlavePort> RespLayer;
+    std::vector<ReqLayer*> reqLayers;
+    std::vector<RespLayer*> respLayers;
 
     /**
      * Declaration of the non-coherent bus slave port type, one will
@@ -207,6 +209,8 @@ class NoncoherentBus : public BaseBus
 
     NoncoherentBus(const NoncoherentBusParams *p);
 
+    virtual ~NoncoherentBus();
+
     unsigned int drain(DrainManager *dm);
 
     /**