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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-09-09 14:40:19 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-09-09 14:40:19 -0400
commit6dc599ea9bae9cb56ca81094b37009f5a14ebdff (patch)
tree6fa3f64eaff474822ebb1917c87f1413bea43e00 /src/mem/packet.cc
parent71aca6d29e686ecdec2828c8be1989f74d9b28d3 (diff)
downloadgem5-6dc599ea9bae9cb56ca81094b37009f5a14ebdff.tar.xz
mem: fix functional accesses to deal with coherence change
We can't just obliviously return the first valid cache block we find any more... see comments for details.
Diffstat (limited to 'src/mem/packet.cc')
-rw-r--r--src/mem/packet.cc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 001725e66..5eb2ecc4b 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -179,7 +179,6 @@ Packet::checkFunctional(Printable *obj, Addr addr, int size, uint8_t *data)
if (func_start >= val_start && func_end <= val_end) {
allocate();
memcpy(getPtr<uint8_t>(), data + offset, getSize());
- makeResponse();
return true;
} else {
// In this case the timing packet only partially satisfies