diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-06-27 12:29:00 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-06-27 12:29:00 -0500 |
| commit | f6f63ec0aa68f631691d9eccc18739722a0a9f17 (patch) | |
| tree | 6d3cd4d0f43381980412ade2ed8266e3d3ba472d /src/mem/packet.cc | |
| parent | 3be4f4b846f991c98fe1909631996c5b58d52437 (diff) | |
| download | gem5-f6f63ec0aa68f631691d9eccc18739722a0a9f17.tar.xz | |
mem: write streaming support via WriteInvalidate promotion
Support full-block writes directly rather than requiring RMW:
* a cache line is allocated in the cache upon receipt of a
WriteInvalidateReq, not the WriteInvalidateResp.
* only top-level caches allocate the line; the others just pass
the request along and invalidate as necessary.
* to close a timing window between the *Req and the *Resp, a new
metadata bit tracks whether another cache has read a copy of
the new line before the writeback to memory.
Diffstat (limited to 'src/mem/packet.cc')
| -rw-r--r-- | src/mem/packet.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 4ff531e80..5b0834285 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -98,11 +98,11 @@ MemCmd::commandInfo[] = /* HardPFResp */ { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), InvalidCmd, "HardPFResp" }, - /* WriteInvalidateReq (currently unused, see packet.hh) */ + /* WriteInvalidateReq */ { SET6(IsWrite, NeedsExclusive, IsInvalidate, IsRequest, HasData, NeedsResponse), WriteInvalidateResp, "WriteInvalidateReq" }, - /* WriteInvalidateResp (currently unused, see packet.hh) */ + /* WriteInvalidateResp */ { SET3(IsWrite, NeedsExclusive, IsResponse), InvalidCmd, "WriteInvalidateResp" }, /* UpgradeReq */ |