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| author | Geoffrey Blake <geoffrey.blake@arm.com> | 2014-09-03 07:42:31 -0400 |
|---|---|---|
| committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2014-09-03 07:42:31 -0400 |
| commit | b404ffde608ce4f2c2175fdc7936f98da5d0998b (patch) | |
| tree | e6ccef9b6556a2c0dab9738e65a780a8e8f6b3d5 /src/mem/packet.cc | |
| parent | 12210ada547fa8ad10a1db4a440c25f6679809bd (diff) | |
| download | gem5-b404ffde608ce4f2c2175fdc7936f98da5d0998b.tar.xz | |
cache: Fix handling of LL/SC requests under contention
If a set of LL/SC requests contend on the same cache block we
can get into a situation where CPUs will deadlock if they expect
a failed SC to supply them data. This case happens where 3 or
more cores are contending for a cache block using LL/SC and the system
is configured where 2 cores are connected to a local bus and the
third is connected to a remote bus. If a core on the local bus
sends an SCUpgrade and the core on the remote bus sends and SCUpgrade
they will race to see who will win the SC access. In the meantime
if the other core appends a read to one of the SCUpgrades it will expect
to be supplied data by that SCUpgrade transaction. If it happens that
the SCUpgrade that was picked to supply the data is failed, it will
drop the appended request for data and never respond, leaving the requesting
core to deadlock. This patch makes all SC's behave as normal stores to
prevent this case but still makes sure to check whether it can perform
the update.
Diffstat (limited to 'src/mem/packet.cc')
| -rw-r--r-- | src/mem/packet.cc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc index faa9d9a53..4ff531e80 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013 ARM Limited + * Copyright (c) 2011-2014 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -115,12 +115,13 @@ MemCmd::commandInfo[] = /* UpgradeResp */ { SET3(NeedsExclusive, IsUpgrade, IsResponse), InvalidCmd, "UpgradeResp" }, - /* SCUpgradeFailReq: generates UpgradeFailResp ASAP */ - { SET5(IsInvalidate, NeedsExclusive, IsLlsc, - IsRequest, NeedsResponse), + /* SCUpgradeFailReq: generates UpgradeFailResp but still gets the data */ + { SET6(IsRead, NeedsExclusive, IsInvalidate, + IsLlsc, IsRequest, NeedsResponse), UpgradeFailResp, "SCUpgradeFailReq" }, - /* UpgradeFailResp */ - { SET2(NeedsExclusive, IsResponse), + /* UpgradeFailResp - Behaves like a ReadExReq, but notifies an SC + * that it has failed, acquires line as Dirty*/ + { SET4(IsRead, NeedsExclusive, IsResponse, HasData), InvalidCmd, "UpgradeFailResp" }, /* ReadExReq */ { SET5(IsRead, NeedsExclusive, IsInvalidate, IsRequest, NeedsResponse), @@ -136,7 +137,7 @@ MemCmd::commandInfo[] = { SET6(IsWrite, NeedsExclusive, IsLlsc, IsRequest, NeedsResponse, HasData), StoreCondResp, "StoreCondReq" }, - /* StoreCondFailReq: generates failing StoreCondResp ASAP */ + /* StoreCondFailReq: generates failing StoreCondResp */ { SET6(IsWrite, NeedsExclusive, IsLlsc, IsRequest, NeedsResponse, HasData), StoreCondResp, "StoreCondFailReq" }, |