rename store conditional stuff as extra data so it can be used for conditional swaps as well

Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656

1 files changed, 11 insertions, 3 deletions

diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index dde6c00d5..14d08db1b 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -94,7 +94,13 @@ MemCmd::commandInfo[] =
             ReadExResp, "ReadExReq" },
     /* ReadExResp */
     { SET4(IsRead, IsInvalidate, IsResponse, HasData),
-            InvalidCmd, "ReadExResp" }
+            InvalidCmd, "ReadExResp" },
+    /* SwapReq -- for Swap ldstub type operations */
+    { SET4(IsReadWrite, IsRequest, HasData, NeedsResponse),
+        SwapResp, "SwapReq" },
+    /* SwapResp -- for Swap ldstub type operations */
+    { SET3(IsReadWrite, IsResponse, HasData),
+        InvalidCmd, "SwapResp" }
 };
 
 
@@ -238,9 +244,11 @@ operator<<(std::ostream &o, const Packet &p)
     if (p.isRead())
         o << "Read ";
     if (p.isWrite())
-        o << "Read ";
+        o << "Write ";
+    if (p.isReadWrite())
+        o << "Read/Write ";
     if (p.isInvalidate())
-        o << "Read ";
+        o << "Invalidate ";
     if (p.isRequest())
         o << "Request ";
     if (p.isResponse())