diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:01:21 -0400 |
---|---|---|
committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:01:21 -0400 |
commit | 28e9641c2cf063d8ee1eba9f440dfcda9c82d965 (patch) | |
tree | 27d82f9251fe5b6eb5d4daa94c6b2af00f324229 /src/mem/packet.cc | |
parent | 780aa0a0ebb765781a31d0fb58257b1efb1f324a (diff) | |
download | gem5-28e9641c2cf063d8ee1eba9f440dfcda9c82d965.tar.xz |
Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
Diffstat (limited to 'src/mem/packet.cc')
-rw-r--r-- | src/mem/packet.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc index a16e590e3..46c771c48 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -150,7 +150,7 @@ fixPacket(Packet *func, Packet *timing) Addr timingStart = timing->getAddr(); Addr timingEnd = timing->getAddr() + timing->getSize() - 1; - assert(!(funcStart > timingEnd || timingStart < funcEnd)); + assert(!(funcStart > timingEnd || timingStart > funcEnd)); if (DTRACE(FunctionalAccess)) { DebugOut() << func; |