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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-06-27 12:29:00 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-06-27 12:29:00 -0500 |
| commit | f6f63ec0aa68f631691d9eccc18739722a0a9f17 (patch) | |
| tree | 6d3cd4d0f43381980412ade2ed8266e3d3ba472d /src/mem/packet.hh | |
| parent | 3be4f4b846f991c98fe1909631996c5b58d52437 (diff) | |
| download | gem5-f6f63ec0aa68f631691d9eccc18739722a0a9f17.tar.xz | |
mem: write streaming support via WriteInvalidate promotion
Support full-block writes directly rather than requiring RMW:
* a cache line is allocated in the cache upon receipt of a
WriteInvalidateReq, not the WriteInvalidateResp.
* only top-level caches allocate the line; the others just pass
the request along and invalidate as necessary.
* to close a timing window between the *Req and the *Resp, a new
metadata bit tracks whether another cache has read a copy of
the new line before the writeback to memory.
Diffstat (limited to 'src/mem/packet.hh')
| -rw-r--r-- | src/mem/packet.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh index f93725fcb..155a7ff82 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -91,14 +91,6 @@ class MemCmd HardPFReq, SoftPFResp, HardPFResp, - // WriteInvalidateReq transactions used to be generated by the - // DMA ports when writing full blocks to memory, however, it - // is not used anymore since we put the I/O cache in place to - // deal with partial block writes. Hence, WriteInvalidateReq - // and WriteInvalidateResp are currently unused. The - // implication is that the I/O cache does read-exclusive - // operations on every full-cache-block DMA, and ultimately - // this needs to be fixed. WriteInvalidateReq, WriteInvalidateResp, UpgradeReq, |