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authorAndreas Hansson <andreas.hansson@arm.com>2015-11-06 03:26:43 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-11-06 03:26:43 -0500
commit7433d77fcf74ddcd6052a60e0251a1d5d1a46e44 (patch)
tree5e6fec96caf87968ce5e826320794c0d83a5dee5 /src/mem/packet.hh
parentafa252b0b962be0192b6badf81d2d39ec4f40e4f (diff)
downloadgem5-7433d77fcf74ddcd6052a60e0251a1d5d1a46e44.tar.xz
mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to allow clean writebacks. This functionality is crucial, especially when having exclusive (victim) caches. For example, if read-only L1 instruction caches are not sending clean writebacks, there will never be any spills from the L1 to the L2. At the moment the cache model defaults to not sending clean writebacks, and this should possibly be re-evaluated. The implementation of clean writebacks relies on a new packet command WritebackClean, which acts much like a Writeback (renamed WritebackDirty), and also much like a CleanEvict. On eviction of a clean block the cache either sends a clean evict, or a clean writeback, and if any copies are still cached upstream the clean evict/writeback is dropped. Similarly, if a clean evict/writeback reaches a cache where there are outstanding MSHRs for the block, the packet is dropped. In the typical case though, the clean writeback allocates a block in the downstream cache, and marks it writable if the evicted block was writable. The patch changes the O3_ARM_v7a L1 cache configuration and the default L1 caches in config/common/Caches.py
Diffstat (limited to 'src/mem/packet.hh')
-rw-r--r--src/mem/packet.hh32
1 files changed, 21 insertions, 11 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index f33ee120d..d1c285f04 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -86,7 +86,8 @@ class MemCmd
ReadRespWithInvalidate,
WriteReq,
WriteResp,
- Writeback,
+ WritebackDirty,
+ WritebackClean,
CleanEvict,
SoftPFReq,
HardPFReq,
@@ -144,6 +145,7 @@ class MemCmd
IsRequest, //!< Issued by requester
IsResponse, //!< Issue by responder
NeedsResponse, //!< Requester needs response from target
+ IsEviction,
IsSWPrefetch,
IsHWPrefetch,
IsLlsc, //!< Alpha/MIPS LL or SC access
@@ -192,6 +194,13 @@ class MemCmd
bool needsExclusive() const { return testCmdAttrib(NeedsExclusive); }
bool needsResponse() const { return testCmdAttrib(NeedsResponse); }
bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
+ bool isEviction() const { return testCmdAttrib(IsEviction); }
+
+ /**
+ * A writeback is an eviction that carries data.
+ */
+ bool isWriteback() const { return testCmdAttrib(IsEviction) &&
+ testCmdAttrib(HasData); }
/**
* Check if this particular packet type carries payload data. Note
@@ -491,6 +500,8 @@ class Packet : public Printable
bool needsExclusive() const { return cmd.needsExclusive(); }
bool needsResponse() const { return cmd.needsResponse(); }
bool isInvalidate() const { return cmd.isInvalidate(); }
+ bool isEviction() const { return cmd.isEviction(); }
+ bool isWriteback() const { return cmd.isWriteback(); }
bool hasData() const { return cmd.hasData(); }
bool isLLSC() const { return cmd.isLLSC(); }
bool isError() const { return cmd.isError(); }
@@ -1008,24 +1019,23 @@ class Packet : public Printable
}
/**
- * Is this request notification of a clean or dirty eviction from the cache.
+ * Does the request need to check for cached copies of the same block
+ * in the memory hierarchy above.
**/
bool
- evictingBlock() const
+ mustCheckAbove() const
{
- return (cmd == MemCmd::Writeback ||
- cmd == MemCmd::CleanEvict);
+ return cmd == MemCmd::HardPFReq || isEviction();
}
/**
- * Does the request need to check for cached copies of the same block
- * in the memory hierarchy above.
- **/
+ * Is this packet a clean eviction, including both actual clean
+ * evict packets, but also clean writebacks.
+ */
bool
- mustCheckAbove() const
+ isCleanEviction() const
{
- return (cmd == MemCmd::HardPFReq ||
- evictingBlock());
+ return cmd == MemCmd::CleanEvict || cmd == MemCmd::WritebackClean;
}
/**