diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
| commit | f24ae2ec2a43a5197934668b6f9638ed118994d8 (patch) | |
| tree | f51c948e2eedae7d6772228ddb2653aa71622674 /src/mem/packet.hh | |
| parent | 57f2b7db11c9a16f3104588c137e6246bd124041 (diff) | |
| download | gem5-f24ae2ec2a43a5197934668b6f9638ed118994d8.tar.xz | |
cache: fail store conditionals when upgrade loses race
Requires new "SCUpgradeReq" message that marks upgrades
for store conditionals, so downstream caches can fail
these when they run into invalidations.
See http://www.m5sim.org/flyspray/task/197
Diffstat (limited to 'src/mem/packet.hh')
| -rw-r--r-- | src/mem/packet.hh | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 17af558b5..2c94da8bd 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2010 Advancec Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -81,7 +82,10 @@ class MemCmd WriteInvalidateReq, WriteInvalidateResp, UpgradeReq, + SCUpgradeReq, // Special "weak" upgrade for StoreCond UpgradeResp, + SCUpgradeFailReq, // Failed SCUpgradeReq in MSHR (never sent) + UpgradeFailResp, // Valid for SCUpgradeReq only ReadExReq, ReadExResp, LoadLockedReq, @@ -111,6 +115,7 @@ class MemCmd { IsRead, //!< Data flows from responder to requester IsWrite, //!< Data flows from requester to responder + IsUpgrade, IsPrefetch, //!< Not a demand access IsInvalidate, NeedsExclusive, //!< Requires exclusive copy to complete in-cache @@ -157,7 +162,8 @@ class MemCmd public: bool isRead() const { return testCmdAttrib(IsRead); } - bool isWrite() const { return testCmdAttrib(IsWrite); } + bool isWrite() const { return testCmdAttrib(IsWrite); } + bool isUpgrade() const { return testCmdAttrib(IsUpgrade); } bool isRequest() const { return testCmdAttrib(IsRequest); } bool isResponse() const { return testCmdAttrib(IsResponse); } bool needsExclusive() const { return testCmdAttrib(NeedsExclusive); } @@ -392,7 +398,8 @@ class Packet : public FastAlloc, public Printable inline int cmdToIndex() const { return cmd.toInt(); } bool isRead() const { return cmd.isRead(); } - bool isWrite() const { return cmd.isWrite(); } + bool isWrite() const { return cmd.isWrite(); } + bool isUpgrade() const { return cmd.isUpgrade(); } bool isRequest() const { return cmd.isRequest(); } bool isResponse() const { return cmd.isResponse(); } bool needsExclusive() const { return cmd.needsExclusive(); } |