diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:49 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:49 -0500 |
| commit | 5d029463eef3cfafa507dacadccd33402f82029a (patch) | |
| tree | d2549fad3b8d6e647b0f9cf9a06887346cb65902 /src/mem/packet.hh | |
| parent | e3b19cb294c98466a431950888045c6b5d24b675 (diff) | |
| download | gem5-5d029463eef3cfafa507dacadccd33402f82029a.tar.xz | |
cpu, mem: Make software prefetches non-blocking
Previously, they were treated so much like loads that they could stall
at the head of the ROB. Now they are always treated like L1 hits.
If they actually miss, a new request is created at the L1 and tracked
from the MSHRs there if necessary (i.e. if it didn't coalesce with
an existing outstanding load).
Diffstat (limited to 'src/mem/packet.hh')
| -rw-r--r-- | src/mem/packet.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 0c6abe909..f93725fcb 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -196,6 +196,10 @@ class MemCmd bool hasData() const { return testCmdAttrib(HasData); } bool isReadWrite() const { return isRead() && isWrite(); } bool isLLSC() const { return testCmdAttrib(IsLlsc); } + bool isSWPrefetch() const { return testCmdAttrib(IsSWPrefetch); } + bool isHWPrefetch() const { return testCmdAttrib(IsHWPrefetch); } + bool isPrefetch() const { return testCmdAttrib(IsSWPrefetch) || + testCmdAttrib(IsHWPrefetch); } bool isError() const { return testCmdAttrib(IsError); } bool isPrint() const { return testCmdAttrib(IsPrint); } bool isFlush() const { return testCmdAttrib(IsFlush); } @@ -677,6 +681,8 @@ class Packet : public Printable if (cmd == MemCmd::ReadReq) { if (req->isLLSC()) { cmd = MemCmd::LoadLockedReq; + } else if (req->isPrefetch()) { + cmd = MemCmd::SoftPFReq; } } else if (cmd == MemCmd::WriteReq) { if (req->isLLSC()) { |