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author | Steve Reinhardt <stever@gmail.com> | 2008-01-02 15:22:38 -0800 |
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committer | Steve Reinhardt <stever@gmail.com> | 2008-01-02 15:22:38 -0800 |
commit | 6c5a3ab8b28ae14e1f1c37076b7370b37c70de62 (patch) | |
tree | d89626ebae1a7b4a14f41fe6b33d01dbcb78bdc2 /src/mem/packet.hh | |
parent | bf9b3821bda5f534a44b176c0ed738a17cb9b80a (diff) | |
download | gem5-6c5a3ab8b28ae14e1f1c37076b7370b37c70de62.tar.xz |
Add ReadRespWithInvalidate to handle multi-level coherence situation
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us. We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A. This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.
--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
Diffstat (limited to 'src/mem/packet.hh')
-rw-r--r-- | src/mem/packet.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 30ef71507..05442b369 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -66,6 +66,7 @@ class MemCmd InvalidCmd, ReadReq, ReadResp, + ReadRespWithInvalidate, WriteReq, WriteResp, Writeback, |